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TUSB4041I: Unclear requirements for power up sequence

Part Number: TUSB4041I


Tool/software:

Hi,

I have some doubts concerning TUSB4041I power-up sequence. 

It is described in "TUSB4041I Four-Port USB 2.0 Hub" Manual (SLLSEK3E –JULY 2015–REVISED SEPTEMBER 2017 ), page 10 

I followed the reference design - EVB: https://www.ti.com/lit/ug/sllu227a/sllu227a.pdf?ts=1739296190986&ref_url=https%253A%252F%252Fwww.google.com%252F

where chain of power regulators is used:

5V -> 3v3 -> 1v1

As it was there I also connected GRSTn to GND with 1uF capacitor.

I see some incosistency in that cited documentation and solution in the EVB:

  1. chain of power supply regulation in the EVB does not assure that 1v1 supply comes before 3v3 (1v1 power is regulated from 3v3), 
  2. above is inconsistent with requirement in the note [2] in chip manual,
  3. input GRSTz is pulled up to 3v3 rail if I properly read documentation, isn't it?
  4. documentation states that low level on GRSTz (i.e. asserted GRST) forces the chip to be non-fuctional ("When the GRSTz pin is asserted, the device is completely nonfunctional.")

(i) I worry that circuit in the EVB does not provide proper sequence of power-up,

(ii) Why is the requirement [2] in chip manual if GRSTz is kept low from power-on by capacitor to ground on the pin?

(iii) Is the requrement [2] in chip manual correct? It looks for me like it is opposite condition. 

Kind regards,

Piotr Romaniuk

  • Hi  Piotr:

      for power on sequence:

    1: if 1.1v is up early than 3.3v, then  there is no power on sequence, an external cap on GRSTz should be enough.

    2: if 3.3v is up early than 1.1v, then you may need external control on GRStz that make sure to keep GRStz low at least 3ms after both  1.1v and 3.3v are stable.

    Best

    Brian

  • Hi Brian,

    thank you for information. I measured signals on power pins at start up.

    Figure 1. power start up sequence - power supply rails

    Figure 2. power start up sequence - power supply rails of the chip and GRSTn signal

    As can be seen in Figure 1  The supply voltage 3.3V rises before 1.1V.

    A capacitor of 1uF is connected between GRSTn input of the chip and GND, the voltage on it is shown in Figure 2 (top panel).

    The circuit was taken from the evaluation board. 

    Of course, these conditions does not satisfy requirement 2. from chip datasheet: there is only capacitor on GRSTn and 1.1V is not 10us befor 3.3V.

    Why is it necessary that there is 1.1V before 3.3V, even if GRSTn is kept low? 

    Regards,

    Piotr Romaniuk

  • GRSTz is internally pulled up 3.3v, so GRSTz signal will go high after 3.3v is up. to make sure GRSTz keep low 3ms after 1.1v and 3.3v stable:

    1: it's batter 1.1v is up before or same as 3.3v.

    2; adding big value CAP on GRSTz pin to Gnd.

    Best

    Brian

  • Hi Brian,

    we installed hundreds of boards with TUSB4041 as part of our power electronics devices. The circuit with this USB hub was taken from Texas Instuments reference design. We accidentally discovered that this design does not meet the requirement from the datasheet:

    "(2) [...] GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 μs before the VDD33."

    The above oscillograms are the proof.

    The requirement was specified for a reason. I need to know it in order to understand what consequences can be expected. 
    This is reliability and risk assesment.

    Regards,
    Piotr Romaniuk

  • Hi Piotr:

      Most important  that GRSTz should be low at least 3ms after 1.1v and 3.3v are stable. other sequence between 1.1v and 3.3v is not that matters.

      Did you see any issue for your system?

    Best

    Brian

  • Hi Brian,

    No, I see no issues.
    I am still woried about that "10us". Can you find out who wrote it and why?
    There can be some circumstances where it is important and as I suspect drive to no reset condition or lockup.

    Regards,
    Piotr Romaniuk

  • sure, let me check with our system guy.

    Best

    Brian