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TDES960: Is sleep is required between SerDes register

kanna
Intellectual 335 points

Part Number: TDES960

Tool/software:

Hi,

I am configuring the following deserializer registers before enabling the stream on the Xavier NX SOM:

  • CSI_PORT_SEL (0x32)
  • CSI_CTL (0x33)
  • FWD_CTL1 (0x20)

Is it necessary to include a delay between writing to these registers?