DS125DF111: How to Generate Recovered Clock Rate Synchronized with Re-timed Data output

Chandrakasan Ramesh

Prodigy 90 points

Part Number: DS125DF111
Other Parts Discussed in Thread: DS250DF230

Tool/software:

When sampling the Data in to the FPGA , We need recovered clock ( line rate) and re timed data.

After setting the CDR bit,

To alien the clock phase with the Data , i need to generate the line rate clock synchronized with internal VCO.

Lock signal is available .

Pls suggest

Ramesh

6 months ago

0 David Waier 6 months ago

TI__Mastermind 20901 points

Hi Ramesh,

Today (Feb 17) is a holiday in the US. The support team will get back to you tomorrow regarding your question.

Best,

David

0 Lucas Wolter 6 months ago in reply to David Waier

TI__Mastermind 27910 points

Hi Ramesh,

DS125DF111 does not have the functionality to output recovered clock signal. It can only output the retimed data signal.

The only retimer we have available which can output recovered clock is DS250DF230. This retimer supports 19.6 to 25.8Gbps + divide-by-2 and divide-by-4 subrates.

Best,

Lucas

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DS125DF111: How to Generate Recovered Clock Rate Synchronized with Re-timed Data output