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TCAL6416: The bevaior of INT pin and interrupt mask registers

Shunsuke Yamamoto
Expert 7671 points
Part Number: TCAL6416

Tool/software:

Hi team,

I don't quit understand the relationship between INT pin and interrupt mask registers and interrupt status registers. When the interrupt mask register is set to 0 and the input changes state from 0 to 1, the INT pin is asserted to low. Is my understanding correct?

The condition of INT pin is deasserted which means the INT pin is asserted high is the timing when the input changes state from 1 to 0. Is my understanding correct? 

Best regards,

Shunsuke Yamamoto

 

  • 0
    TI__Mastermind 47328 points

    Yamamoto-San,

    Shunsuke Yamamoto said:
    I don't quit understand the relationship between INT pin and interrupt mask registers and interrupt status registers. When the interrupt mask register is set to 0 and the input changes state from 0 to 1, the INT pin is asserted to low. Is my understanding correct?

    Default state of interrupt mask register is set to "1" meaning the interrupt on all INPUTs are disabled. 

    To enable the interrupt on a pin, the bit in the interrupt mask register needs to be set to "0". 

    If the input changes state like you said from 0 to 1, the /INT pin should assert LOW. You are correct. 

    Shunsuke Yamamoto said:
    The condition of INT pin is deasserted which means the INT pin is asserted high is the timing when the input changes state from 1 to 0. Is my understanding correct? 

    INT pin releases HIGH (since Open-drain output). So if the input changes back to its original state from 1 to 0 before the interrupt is cleared, the interrupt will be lost. 

    Now if the input latch registers (0x44 and 0x45) are used, then the input state change can be latched which will keep the interrupt on /INT asserted until the input port register is read meaning that the interrupt is not lost. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    TI__Expert 7671 points

    Hi Tyler-san,

    Thank you for the reply.

    Regarding the datasheet, the sentence below is written.

    "Resetting the interrupt circuit is achieved when data on the port is changed back to the original setting or when data is read from the port that generated the interrupt."

    When data is read from the port geneated the intrrupt means the registers 0x00h and 0x01h are read. Is my understanding correct?

    After resetting the interrupt circuit, the INT output gets HIGH. Is my understanding correct?

    Best regards,

    Shunsuke Yamamoto

  • 0 in reply to Shunsuke Yamamoto
    TI__Mastermind 47328 points

    Yamamoto-san,

    If input port register 0 - 0x00 caused the interrupt, and you read input port register 1 - 0x01, then the interrupt will not be cleared. The interrupt will only clear if the 0x00 register is read. 

    Correct. After resetting the interrupt circuit, the INT output releases HIGH to indicate that an interrupt is no longer being asserted. This requires a PU resistor on /INT. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    TI__Expert 7671 points

    Hi Tyler-san,

    Thank you for the reply. The interrupt will only clear if the 0x00 register is read. Is this correct?

    I guess the interrupt will clear if both the register 0 and the register 1 are read. This is correct operation.

    Best regards,

    Shunsuke Yamamoto

  • +1 in reply to Shunsuke Yamamoto
    TI__Mastermind 47328 points

    Yamamoto-san,

    Interrupt may clear if only 0x00 register is read.

    If register 0x01 caused the interrupt, a read of register 0x00 will not clear the interrupt. 

    To ensure that interrupt always clears, it is best practice to read both registers 0x00 and 0x01. 

    Regards,

    Tyler