DP83822I: Issue accessing the PHY address

Hi Koshi,

Thank you for your query. First, I wanted to understand the customer setup a little better

What kind of MII interface is the customer using to connect the processors to the PHY?

What VDDIO Voltage are they using for this setup?

Is customer able to get external MDIO access? If so, can they check if they can read the registers through that? Particularly, I wanted to take a look at the registers 0x467/0x468 for the strap values. 

Best,

Vivaan

Hi Vivaan-san,

MII interface:
 - DRA821 to DP83822I: RMII
 - AM2432 to DP83822I: MII
    *Both case, when the RX_D3 is open for MODE1, Processor can not access the DP83822I by PHY_ADD="00000".

VDDIO voltage:
 - VDDIO = AVD = VSYS_3V3 = 3.3V

When the RX_D3 has external pullup 10kΩ and pulldown 2.4kΩ for MODE2 and Processor can access the DP83822I by PHY_ADD="00000",
 - 0x467: 0x03F3
 - 0x468: 0x0004

When the RX_D3 is open for MODE1 and Processor can not access the DP83822I by PHY_ADD="00000",
Since register access is not possible in this case, values of 0x467 and 0x468 cannot be obtained.
You mentioned "External MDIO access",  dose it mean that MDIO access is performed from other than the CPU?

When the RX_D3 is open for MODE1, they tested PHY_ADD="10000" too, but Processor can not access the DP83822I either.

Do you understand what is causing this issue accessing the PHY address?

Best Regards,

Koshi Ninomiya

Hi Ninomiya-san, 

Thank you for clarifying this information. 

I can see in the scope shots that the voltage measured on RX_D3 with the resistors removed is reading as ~0V, but I wanted to test with only the 10k PD placed, and the PU removed, just as a sanity check to make sure that the pin is indeed being pulled down.

I also wanted to confirm whether placing these 2 resistors back restores the lost MDIO communication or not?

Koshi Ninomiya said:

You mentioned "External MDIO access",  dose it mean that MDIO access is performed from other than the CPU?

In some cases, we add jumpers on the MDIO lines in case we need to externally access them on our EVMs, just wanted to see if that was an option here, but it looks like it is not. We still have other methods of seeing some PHY status. 

Can customer see the link LED toggling when connecting a link partner to the DUT? This would help us understand if it is only the MDIO access that is affected or something bigger within the PHY itself.

Best,

Vivaan

Hi Vivaan-san,

While the customer continues to verify this issue, even if the RX_D3 pin setting is set to the same MODE2, there are some boards that can access the PHY registers and some boards that cannot, and the cause may not be the difference in the RX_D3 pin setting.
For this reason, they measured the waveforms of MDIO and MDC during power-on on two boards.

Please review an attached below, at <2025/2/25> section.

2553.DP83822I RX_D3 PHY_AD4 issue.xlsx

When the Processor can not access the DP83822I, the data from the PHY seems to be outputtint "1".
In the waveform where the DP83822I has been successfully detected, it appears that the PHY outputs "0" (assuming it is its own address).
Another point of concern is that the high level when the PHY is driving the MDIO is slightly lower, and the PHY side seems to be driving the MDIO even before the MDC is output at the beginning.
They would like to know what causes can be inferred from these?

Best Regards,

Koshi Ninomiya

Hi Ninomiya-san,

This is unexpected behaviour. Since this is the start of data transmission, I believe that the SoC/MAC is driving the MDIO pin, not the PHY. The PHY sets the MDIO in a High-Z state initially to act as an input to the SoC's commands.

I would like to investigate whether its the SoC driving the MDIO incorrectly.

Best,

Vivaan

Hi Vivaan-san,

Could you let me know how to investigate whether the SoC is driving the MDIO incorrectly?

Best Regards,

Koshi Ninomiya