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DS90UB960-Q1: Video Output Interface and Clock Synchronization with AM62Ax and DS90UB953

Rishabh mishra
Prodigy 120 points
Part Number: DS90UB960-Q1

Tool/software:

Hi Team,

I have some queries regarding this architecture:

Q1. We are using different crystals/oscillators for this architecture individually. Is this acceptable, or do we need to synchronize the same clock for this application concerning the DS90UB953( Non-synchronous).

Q2. Is the structure for video output appropriate?

Q3. Can we compress the  Port 2 CSI-2 upto 832 Mbps per lane for DS90UB953 compatibility

Q4.How do both camera data streams come on MIPI CSI-2 in term of packet or media 

  • 0
    TI__Mastermind 26410 points

    Hello,

    Please find feedback below:

    1. As long as the devices are operating in non-synchronous mode, using a separate oscillator for each FPD-Link device is acceptable. 
    2. Can you clarify what you mean by the video output structure? If you are talking about the system architecture of a deserializer CSI port being fed to another serializer, this is okay as long as the bandwidth of the receiving serializer is not violated. Please note that the receiving serializer requires a partner deserializer.
    3. No, the 960 CSI ports operate at fixed nominal rates. The port can only operate at 400Mbps, 800Mbps, 1200Mbps, or 1600Mbps per lane.
    4. The aggregated output of the data streams is dependent on the chosen forwarding method. By default the video packets will be output round robin style, where as each packet arrives on an RX port it will be forwarded to the CSI port. The order of the packets will be determined by the order that they are initially received. For other forwarding methods see section 7.4.25 of the 960 device data sheet.