PCA9545A: Questions about the interface timing of the PCA9545APW

Anpeng La

Part Number: PCA9545A

Tool/software:

While debugging the PCA9545A, I noticed that the ack signal is always transmitted after SCL goes high. Why is this the case?

7 months ago

0 Clemens Ladisch 7 months ago

Guru 317370 points

The eight data bits and the ACK/NACK bit are sampled at the rising edge of SCL.

In this example, the ACK bit is sampled at 196 µs. The ACK bit was driven low by the slave, while the following low level is driven by the master in order to send the stop condition. While the switch-over between slave and master happens, the SDA line might go high for a short time; this is normal and not a problem.

0 Anpeng La 7 months ago in reply to Clemens Ladisch

Prodigy 10 points

Do you mean that I should detect the ACK between the rising edge and the falling edge of the 9th SCK after I2C is started?

0 Clemens Ladisch 7 months ago in reply to Anpeng La

Guru 317370 points

Not "between", but at the rising edge. What matters is the state at the single point of time marked with the arrow.

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PCA9545A: Questions about the interface timing of the PCA9545APW