TCAN4551-Q1: TCAN4551-Q1

Hello Abhishek,

The issue is likely still a crystal related issue, but not in the sense that the crystal will fail to oscillate.  Instead, the high temperatures is causing the oscillation amplitude voltage on the OSC2 pin to change such that the lowest voltage level crosses low enough for the single-ended detection comparator that is used to detect a "grounded" pin to trigger and is causing the device to switch to single-ended mode.  When this occurs, the crystal amplifier is disabled and the device stops sourcing current to the crystal out of the OSC1 pin and expects a single-ended clock to be input on the OSC1 pin instead.  Because this is not present, the device does not have a functioning clock and communication issues can occur. 

The overall capacitive load (CL) on the crystal decreases with increasing temperatures due to the change in parasitic capacitance (which is not temperature stable like ceramic caps) and causing the lowest voltage level to cross below the single-ended mode threshold that is between 90mV and 150mV.  Your are using 3.3pF ceramic caps to add to the parasitic capacitance of the PCB trace and OSC1/2 pins to create the total CL.  But because the parasitic capacitance doesn't have a stable temperature coefficient, the CL will vary with temperature and some margin needs to be factored into the system and this issues is usually seen when a low value of caps is used such as 3.3pF.

There is also some amount of device to device variance in the strength of the transconductance amplifier that also requires some margin in the design.  The devices that generally have issues will have stronger amplifiers causing more current to be sourced to the crystal and increasing the drive level (DL) and causing a larger oscillation voltage.

Please see the TCAN455x Clock Optimization and Design Guidelines Application Report (Link) for more information.

To stabilize the operation, we need to reduce the OSC2 voltage peak-to-peak amplitude, and prevent the voltage on the OSC2 pin from dropping below 150mV.

• A series dampening resistor placed between the OSC1 pin and the crystal will reduce the current flow through the crystal and lower the amplitude.
• Increasing the value of the load capacitors on the OSC1 and OSC2 pins forms a larger voltage divider between the ESR of the crystal and the reactance of the capacitors.  This does create a small frequency shift, but generally not large enough to violate CAN tolerance requirements.
• Asymmetrically loading more capacitance on the OSC2 pin and less on the OSC1 pin.  This has been simulated and tested to show stable performance and this allows the total CL to remain the same, but creates a larger voltage divider on the OSC2 pin where it is needed to avoid the single-ended detection comparator

Regards,

Jonathan

Hi Jonathan ,

Thanks for the detailed explanation .

1. We observed that the crystal is oscillating during the failure (CAN) , Your explanation tells if there is a detection of a single ended clock it will stop sourcing current to the crystal , then why Crystal is still oscillating ?

2. Both Amplitudes OSC1 & OSC2 are more like 1.2V ( See attached report -  ME25026 -Preliminary Report.pdf ) , How does single ended detection works( Differential voltage , Phase Shift or OSC2 Only ) ? . Also can you mark this on Fig 3.1 from the application note slla549.

3.From the Chat - To stabilize the operation, we need to reduce the OSC2 voltage peak-to-peak amplitude, and prevent the voltage on the OSC2 pin from dropping below 150mV - Why to reduce the voltage if we want to avoid to be below 150mV ?

4.We have no damping resistor in our product how the damping resistor works , the crystal supplier measured perfect current and power condition for the crystal and is working fine .

Also is it OK to have a call / discussion on the same . This would be highly recommended !

Thanks  Regards

Abhishek

PH- +91 9611419002

Email - michael.irsigler@continental-corporation.com

            abhishek.m.v@continental-corporation.com

Hi Abhishek,

I can address your questions through email.

Regards,

Jonathan