Other Parts Discussed in Thread: DP83869, DP83869EVM
Tool/software:
When the DP83869 is used with a 25 MHz crystal containing a load capacitance of 20 pF, according to the datasheet this is within specifications. (15 to 40 pF) During testing a lot of packet loss was seen. When the DP83869 is fed with an external clock, everything seems fine, so clearly there is something odd going on within the crystal circuit.
When looking into the snla290 application note about Selection and specification of crystals for Texas Instruments ethernet physical, some more tuning is performed. Lowering the load capacitors raised the clock output frequency. The reliability between two systems with the same load capacitor values went up, but failed with standard copper Ethernet interfaces of other devices. Nearing the capacitance needed for the 25 MHz made the device unstable again.
When reading the snla290 application note more thoroughly a discrepancy was discovered between the datasheet and application note on the load capacitance values for the crystal. The datasheet states a load capacitance of 15 to 40 pF, the application note recommends a load capacitance value of 8 to 20 pF. Also the reference design DP83869EVM is using a crystal with a load capacitance of 12 pF, which, according to the datasheet, is below the specifications.
Changing the crystal for one with a capacitance of 12 pF, and matching the load capacitors to match this value (of course compensated for the stray capacitance) seems to result in a stable connection, without any packet loss. (Tested both against a standard copper Ethernet interface and a matched DP83869)
This configuration is still under test, but still seems promising. I'd really like someone from TI to conform if the datasheet contains a faulty stated load capacitance range, or if the application note and reference design are wrong here. Because according to the datasheet, this circuit is now running outside of the specifications.
Thanks in advance!
