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DS125DF410: Master mode and slave mode design

PANKAJ CHOUDHARY
Prodigy 30 points
Part Number: DS125DF410
Other Parts Discussed in Thread: TS3A4741

Tool/software:

In our design we are using 4 number of  DS125DF410 IC to cater for 16 10G transceivers of Agilex 7 FPGA.

We are interested to provide both master and slave configuration mode in our design. In the datasheet we are not finding connection diagram when both modes are required. We could see the connection diagram (page no 12) for master mode only. Also I need to understand how to connect READ_EN(pin no 44), ALL_DONE(pin no 41), EN_SMB(pin no .20) pins for our above requirement.

In the Eval board schematic we are unable to understand the connectivity of above three pins mentioned. Kindly share the connection diagram,write up and schematic  as per our requirement.

  • 0
    TI__Mastermind 27800 points

    Hi Pankaj,

    When DS125DF410 is configured for SMBus master mode, it begins reading its configuration from the EEPROM when the READ_EN input pin is pulled low. After it finishes reading its configuration, the ALL_DONE output pin is pulled low and the device reverts to SMBus slave mode, meaning registers can be accessed and modified by a controller device. To configure DS125DF410 in SMBus master mode, leave the EN_SMB pin floating.

    Each retimer on the same bus needs to have a unique SMBus address. To prevent bus contention from multiple retimers attempting to read their configuration at the same time, the READ_EN pin and ALL_DONE pins should be daisy chained.

    • Tie READ_EN of the first retimer to GND.
    • Tie ALL_DONE of the first retimer to READ_EN of the second retimer.
    • Tie ALL_DONE of the second retimer to READ_EN of the third retimer.
    • Tie ALL_DONE of the third retimer to READ_EN of the fourth retimer.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 30 points

    Hi Lucas,

    Thanks for the reply, explanation suggested is helpful , but still I have a doubt on EN_SMB(Pin no 20), as i have understood from the datasheet it has to be kept floating for operating in master mode. Now when ALL_DONE(pin no 41) pin is pulled low after the initial configuration is done in master mode , indicating the complation of initial configuration from EEPROM. To switch over from master to slave mode should we drive EN_SMB high only after monitoring ALL_DONE pin which is terminated at Agilex FPGA? 

    When i observed development board schematic TS3A4741 (2-channel analog switch) is kept . In our case i am connecting IN(pin no 3)  pin to Agilex FPGA from which we can control the EN_SMB of  DS125DF410 IC. 

    Please comment if our approach is correct  for enabling both the modes in DS125DF410 IC.

    Regards,

    Pankaj

  • 0 in reply to PANKAJ CHOUDHARY
    TI__Mastermind 27800 points

    Hi Pankaj,

    You do not need to make any change to the EN_SMB pin, it should be left floating for the entire duration of operation. When EEPROM load completes and ALL_DONE pin is pulled low, DS125DF410 will automatically revert to SMBus slave mode.

    Best,

    Lucas