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Original question:

[FAQ] RGMII Timing - Align and Shift mode

DP83TC812R-Q1: RGMII Timing setting

Jing Liang
Prodigy 160 points

Tool/software:

May I know if I use 100baseT1，what need to be config for RGMII? I currently set RGMII enabled and align mode and during strap setting since SOC MAC mode can not set delay time.

I look into the datasheet there is no example and no local FAE can support this topic.

  1. if I set RGMII align mode what is delay status of power up after strap take effect?
  2. what is the differences between  RGMII (TX and RX Internal Delay Mode) and  RGMII (Align Mode)?
  3. if I set dll_tx_delay_ctrl_rgmii_sl =5ns by MDIO way, is there any problem?
  4. Do I  need to set cfg_rgmii_tx_clk_shift_sel? if clock is delay 90 degree, Sicne the clock is 40ns, clk is delay 10ns. Do I need to set addtional delay by dll_tx_delay_ctrl_rgmii_sl=5ns? if yes then total delay would be 15ns?

  • 0
    TI__Genius 9209 points

    Hi Jing,

    Jing Liang said:
    if I set RGMII align mode what is delay status of power up after strap take effect?

    when cfg_rgmii_rx_clk_shift_sel[1] = 1h  the clock on PIN is delayed by 2ns relative to RGMII_RX data.

    Jing Liang said:
    what is the differences between  RGMII (TX and RX Internal Delay Mode) and  RGMII (Align Mode)?

    See RGMII output timing for more information. RGMII align mode means there is -750 to 750 ps of skew on the output clock, whereas with RX or TX shift mode enabled, (Internal delay mode) you see a 2 ns delay added.

    Jing Liang said:
    if I set dll_tx_delay_ctrl_rgmii_sl =5ns by MDIO way, is there any problem?

    A minimum of 1ns setup and 1ns hold time must be maintained at the input of the receiver. By default, the value is 7 * 312.5 ps =~ 2ns see dll_tx_delay_ctrl_rgmii_sl and dll_rx_delay_ctrl_rgmii_s. I don't know if there would be a problem with 5 ns but it is generally not recommended to use the device in this way.

    Jing Liang said:
    Do I  need to set cfg_rgmii_tx_clk_shift_sel? if clock is delay 90 degree, Sicne the clock is 40ns, clk is delay 10ns. Do I need to set addtional delay by dll_tx_delay_ctrl_rgmii_sl=5ns? if yes then total delay would be 15ns?

    https://www.ti.com/lit/ug/snla431/snla431.pdf

    See the appnote above and look at this section Reduced Gigabit Media Independent Interface (RGMII)

    The 90 degrees that you see is from an outdated datasheet. Please see an updated datasheet on TI.com. The clock delay is 2ns. 

  • 0 in reply to Nick Peabody
    Prodigy 160 points

    Thanks, for most questions are clear for me,  and if cfg_rgmii_tx_clk_shift_sel=1? then there is 2ns delay, and then if dll_tx_delay_ctrl_rgmii_sl=2.5ns, what is total delay ? 2+2.5ns?

  • 0 in reply to Nick Peabody
    Prodigy 160 points

    May I know if I plan to set RGMII (TX and RX Internal Delay Mode)  RX_D2_strap, RX_D1_strap, RX_D0_strap} ==3'b110
     with default delay setting, do I need to set  cfg_rgmii_tx_clk_shift_sel?

    below description said use this mode when RGMII_TX signal are aligned, so I think RGMII (TX and RX Internal Delay Mode)  does not need to set this register.

    How to understand below logc description? 

    reset_val = 1 else if({RX_D2_strap, RX_D1_strap, RX_D0_strap} ==
    3'b110) reset_val = 1 else reset_val = 0

  • +1 in reply to Jing Liang
    TI__Genius 9209 points

    Hi Jing,

    Jing Liang said:
    Thanks, for most questions are clear for me,  and if cfg_rgmii_tx_clk_shift_sel=1? then there is 2ns delay, and then if dll_tx_delay_ctrl_rgmii_sl=2.5ns, what is total delay ? 2+2.5ns?

    No, it is more like one or the other. You can increase the delay using the delay register, but the default that you get from enabling the shift register is 2ns.

    Jing Liang said:

    How to understand below logc description? 

    reset_val = 1 else if({RX_D2_strap, RX_D1_strap, RX_D0_strap} ==
    3'b110) reset_val = 1 else reset_val = 0

    See this image.

    RX_D2 is MAC[2], RX_D1 is MAC[1] and RX_D0 is MAC[0]

    reset_val indicates the value of the register after turn on. A reset_val of 1 means the bit is activated. The logic indicates what the pullups straps do to the register on power up.

    For example, to enable TX and RX internal delays. Pull RX_D2 high, pull RX_D1 high, and leave RX_D0 floating. (MAC[2] =1) , (MAC[1] = 1), (MAC[0] = 0). See the table above.

    Jing Liang said:
    May I know if I plan to set RGMII (TX and RX Internal Delay Mode)  RX_D2_strap, RX_D1_strap, RX_D0_strap} ==3'b110
     with default delay setting, do I need to set  cfg_rgmii_tx_clk_shift_sel?

    If you use pin strap control to enable the delay in TX and RX you do not need to set the shift register because it will already be set. You also do not have to set the delay register unless you want a longer or shorter delay for some reason.

    Best Regards,

    Nick