DP83869HM: Can we get clock output that recovered from SGMII when DP83869 is in RGMII-to-SGMII bridge mode?

Thank you for your reply.

David (ASIC) Liu said:

There is no register setting documented to bring out SGMII recovered clock for DP83869.

I understand that there are no registers in the documentation.
I would like to know if the DP83869 can output SGMII recovered clock.
Does this mean that the DP83869 does not have the functionality?

Thank you.

Hello,

Thank you for your query. David is OoO and will be able to respond to your query by EoD Tuesday at latest.

Sincerely,

Gerome

Hello,

It's a shame that this feature isn't available.
I'm in trouble because I've built my hardware using the DP83869.

Is there any other way to output the SGMII recovered clock with the DP83869?

I have one more question. The setting for "SyncE 125/5 MHz recovered clock" is not written.
CLK_O_DISABLE in register 0x170 is the clock output setting, but where is the SyncE setting?

Thank you.

Hi,

You can program reg<0x170>[12:8] = 0x04 to get 25MHz syncE clock on CLK_OUT pin of the device.

Thanks

David

Hello,

Thank you for your reply.

David (ASIC) Liu said:

You can program reg<0x170>[12:8] = 0x04 to get 25MHz syncE clock on CLK_OUT pin of the device.

When using RGMII to SGMII bridge mode, if I set register <0x170>[12:8] = 0x04, is the clock that is output the SyncE clock?

Thank you.

Hi,

For register 0x170, the CLK_OUT by default is synchronous to the XI input clock. For SyncE clock, it can be configured to synchronous to MDI Channel A, B, C, or D.

But in the RGMII to SGMII bridge mode, the DP83869 is not using the MDI so the CLK_OUT can not output the SyncE clock.

Thanks

David