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DS90UB928Q-Q1: pin setting

Part Number: DS90UB928Q-Q1


Tool/software:

Hello team,

My customer have some questions for 928. Can you check and give them feedback please?

- CAPI2S

If they don't use digital audio, is it OK not to place C13?

- LFMODE

They want to use default LFMODE=0 setting. Is it possible floating or connecting GND directly?

- CMF

Should they put 0.1uF capacitor? If yes, can you teach me the rating?

-MODE_SEL

Is it possible to connect GND directly if they want MODE_SEL=L? or needs 40.2kOhm pull-down.

Regards,

Youhei MIYAOKA

  • Hi Youhei,

    For the DS90UB928-Q1,

    - CAPI2S

    As indicated by the datasheet, this should always be populated with 4.7µF, regardless of if the I2S is used or not. I do not recommend this should be floating.

    - LFMODE

    While LFMODE pin does have a pulldown internal resistor, it may be recommended to tie this pin to ground to avoid the possibility of noise changing the status from 0 -> 1.

    - CMF

    Yes, this pin requires a 0.1 µF capacitor to GND. In general, these decoupling capacitors should have a lor ESR, a minimum voltage rating of 4x the expected supply, automotive qualification (AEC-Q200 for example), small package sizes, and X7R cap recommended to reduced parasitic effects.

    -MODE_SEL

    The MODE_SEL pin is recommended to have a pulldown resistor, even if the ideal VR4 is intended to be 0V.

    Please let me know if you have any further questions or feedback from the customer!

    Best,

    Miguel

  • Hi Miguel,

    Thanks you for your support. I received additional question below, can you check please?

    - Is it OK to apply voltage to the SDA/SCL pin via the I2C pull-up while no voltage is applied to the VDD of the IC?

    Regards,

    Youhei

  • Hi Youhei,

    The recommendation is to ensure that the PDB rises before performing any I2C transactions.

    Although there is no official recommendation to the sequencing of applying the power to the I2C SCL and SDA lines on the 928 data sheet, in recent devices they have been recommended to enable 3ms after the PDB has reached steady state.

    This is to avoid any misconfiguration of registers or lock-ups on the I2C bus during initialization, but from DC characteristics - as long as the voltages do not exceed these values it should not damage the pins:

    Please let me know if you have any further questions or need any further clarifications!

    Best,

    Miguel