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LM51770: schematic check

Part Number: LM51770


Tool/software:

Hi 

Could you help check below the LM51770 schematic and any need to adjust, Thanks

TI_sch LM51770 TPS4800 (002)-output.pdf複本 LM51770 Buck-Boost Quickstart Tool V1_0_0.xlsm

  • Hi Gareth,

    Please see below my review list and bold marked line items which should be checked again (Note: other info are left here to give an overview of what has been checked)

    (Underlined parts not checked as info is missing)

    Checked with Quickstart Calculator

     

     

    Schematic:

     

    • Rcs in series with inductor and before inductor
    • Check filter for Rcs
      Current sense Resistor Rcs does not have the required filter
    • Check filter for Risns
      Current sense Resistor Risns does not have the filter - recommend to add place holder
    • Connect IMONOUT to VCC if ISNS not used
      Connect ILIMCOMP  to VCC2 if ISNS not used
    • Snubber on SW1 and SW2
      Place Footprint for a snubber at SW1 and SW2
       (they can then be populated in case needed (e.g. due to EMI) without layout change)
      Note: Snubber connect Resistor to GND for better Thermal performance
    • BIAS connected  
      If BIAS is not used connect to GND or VIN of VOUT (do not keep open)
      BIAS can be connected to VIN (if the max ratings of BIAS are not violated) to benefit from the better performance of the LDO on BIAS
      -> recommend to connect to VOUT
    • Add Series Resistor into MOSFET Gate signals lines
      (they can then be replaced in case needed (e.g. due to EMI) without layout change,
      additional option: add a diode in parallel for slow on and fast off.
    • Recommend to use a dedicated gate Resistor for EACH MOSFET
      Note: Good starting value is 3.3Ω and then adjust in when testing out the PCB
    • Voltage rating of MOSFET
      (Have a margin of 30% is recommended)
    • Miller Plateau of MOSFETs
      used MOSFETs need to be logic level MOSFETs - can be seen by Miller Plateau in the range of 2.5V-3.5V
    • UVLO setting relative to lowest input voltage
      UVLO is set to 7V but operating range starts at 9V - relative large distance
    • Cap at VCC (EVM uses: 47uF) : (Datasheet min: 10uF with DC Bias
      please check the cap on Vcc to have the required capacitance considering DC BIAS - we use a 47uF on the EVM
      This Cap most properly will not provide the required capacitance!

    Best regards,

     Stefan