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Original question:

DP83867IS: Debugging SGMII Interface with T1042 Processor and Testing MII Internal Loopback on DP83867IS PHY

DP83867IS: No PING: SGMII communication is not happening

Animesh Garg
Prodigy 30 points
Part Number: DP83867IS

Tool/software:

We are testing the SGMII PHY in our carrier board which have T1042 NXP Power PC on it, the link is being established on the copper side but not on the PHY side, meaning PHY is not getting acknowledgement from the processor on control information as per the SGMII troubleshooting guide.

We have tried to do the soft reset on PHY to provide control information but we couldn't get it.

  • 0
    TI__Mastermind 39855 points

    Hello,

    Can you please share register log of the SGMII registers as well as the strap registers (Reg 0x6E/F) per the troubleshooting guide? Please note these are extended registers and thus need extended register access to read/write properly. 

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 30 points

    => mdio write FSL_MDIO0 0x0 0x0d 0x1f
    =>
    => mdio write FSL_MDIO0 0x0 0x0e 0x6e
    =>
    => mdio write FSL_MDIO0 0x0 0x0d 0x401f
    =>
    => mdio read FSL_MDIO0 0x0 0x6e
    Reading from bus FSL_MDIO0
    PHY at address 0:
    110 - 0x800
    =>
    Reading from bus FSL_MDIO0
    PHY at address 0:
    110 - 0x800
    =>

  • 0 in reply to Animesh Garg
    TI__Mastermind 39855 points

    Hello,

    Thank you for sharing Reg 0x6E. Could you also please share Reg 0x0, 0x1, 0x11, 0x31, 0x37?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 30 points

    Reading from bus FSL_MDIO0
    PHY at address 0:
    0 - 0x1140
    1 - 0x796d
    2 - 0x2000
    3 - 0xa231
    4 - 0x1e1
    5 - 0xc5e1
    6 - 0x6d
    7 - 0x2001
    8 - 0x6801
    9 - 0x300
    10 - 0x3800
    11 - 0x0
    12 - 0x0
    13 - 0x0
    14 - 0x0
    15 - 0x3000
    16 - 0x5848
    17 - 0xaf02
    18 - 0x0
    19 - 0x0
    20 - 0x29c7
    21 - 0x0
    22 - 0x0
    23 - 0x40
    24 - 0x6150
    25 - 0x4444
    26 - 0x2
    27 - 0x0
    28 - 0x0
    29 - 0x0
    30 - 0x2
    31 - 0x0

    => mdio write FSL_MDIO0 0x0 0x0d 0x1f
    =>
    => mdio write FSL_MDIO0 0x0 0x0e 0x37
    =>
    => mdio write FSL_MDIO0 0x0 0x0d 0x401f
    =>
    => mdio read FSL_MDIO0 0x0 0x37
    Reading from bus FSL_MDIO0
    PHY at address 0:
    55 - 0x40
    =>
    Reading from bus FSL_MDIO0
    PHY at address 0:
    55 - 0x40
    =>

  • 0 in reply to Animesh Garg
    TI__Mastermind 39855 points

    Hello,

    It would appear that the PHY is properly configured in SGMII but is not able to link up. Typically, this is either due to signal integrity or the MAC not doing its part to converge on the link. I would suggest measuring the eye at the MAC and ensuring it is acceptable to the MAC's inputs and checking with the MAC if it is properly configured.

    Sincerely,
    Gerome