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DP83822I: No TX_CLK and RX_CLK output under MII Mode

Koshi Ninomiya
Expert 5595 points
Part Number: DP83822I


Tool/software:

Dear Team,

My customer is evaluating the DP83822I on their board. MII Mode is set by Bootstrap, AVD=VDDIO=3..3V power up and 25-MHz reference clock is inputted, however TX_CLK and RX_CLK are not outputted from the PHY to the MAC of Processor.

What are the possible factors for this phenomenon?

Best Regards,

Koshi Ninomiya

  • +1
    TI__Mastermind 25048 points

    Hi,

    This could be a symptom of failed strap setting, link failure, or MPU is not enabling correct MAC interface.

    Please confirm:

    • Register read value of 0x17 (to confirm MII is enabled)
    • Register value of 0x1 (to confirm link up)

    Thank you,

    Evan