TCAN4550: bit errors due to temperature dependence

Hi Nishie,

Yuta Nishie said:

Could you please tell me what possible internal operation may be causing TCAN4550 bit errors due to temperature dependence?

Is it possible that the parasitic capacitance inside the IC changes as the temperature rises, causing the clock mode to change?

Yes, you are correct.  The parasitic capacitance is decreasing with higher temperatures and causing a change to the total capacitive load on the crystal.  A lower capacitance results in a larger oscillation peak-to-peak amplitude which can cause the lowest level of this waveform to drop below the single-ended mode detection comparator on the OSC2 pin that is checking for a "grounded" condition which is needed to place the device into single-ended clock mode. 

Yuta Nishie said:

At this time, the oscillator output is connected to OSC1 and OSC2, but no load capacitance is implemented. The bit error problem was solved by connecting a 10pF capacitor in parallel.

Operating with only parasitic capacitance is only possible with a series dampening resistor located between the OSC1 pin and the crystal to reduce the current flowing through the crystal and dampen or reduce the oscillation waveform amplitude to a level that prevents the device switching to single-ended clock mode.

When the device switches to single-ended clock mode, the transconductance amplifier stops sourcing current to the crystal through the OSC1 pin and expects a single-ended clock to be input on this pin, which isn't provided at CMOS levels.  Therefore, the device does not have a functional clock and the digital core and MCAN controller are paused which results in CAN and SPI bit errors.

After a period of time, the crystal oscillation amplitude decreases because of the losses from the parasitic resistance and the device switches back to crystal mode where current is sourced again and the amplitude starts to increase resulting in a cycle of mode switching between crystal and single-ended modes.

Please review the TCAN455x Clock Optimization and Design Guidelines Application Report (Link) for more information.

To resolve this issue you will need to either add a series dampening resistor between the OSC1 pin and the crystal (which is the preferred solution) or add and increase the value of the two load caps that should be located on each side of the crystal.

Regards,

Jonathan

Hi Nishie-san,

The fundamental goal is to increase the minimum voltage level of the OSC2 waveform to keep it above the 150mV threshold at all times.  This is the maximum threshold on the single-ended mode detection comparator that is used to check the OSC2 pin for a "grounded" condition and switch the device into single-ended clock mode.  Since you are using a crystal, we need to adjust the components to prevent the oscillation amplitude and low level from being near or below this 150mV level.

There are two methods to do this, and they both accomplish this task differently.

One method is to increase the load capacitance.  There is a voltage divider effect created by the ESR of the crystal and the reactance of the load capacitor that essentially establishes the waveform voltage levels.  Increasing the load capacitance can increase the low level of the OSC2 pin voltage, but it also can result in a larger total capacitive load on the crystal which results in a slight frequency shift. 

The other method is to use a series resistor to reduce the amount of current flowing through the crystal and lower the drive level which reduces the oscillation amplitude.  The power dissipated across the crystal results in a mechanical vibration that induces a proportional voltage waveform.  Reducing the current therefore reduces the mechanical vibration resulting in a smaller voltage amplitude.  The benefit to this approach is that the total capacitive load on the crystal is not increased and therefore there is no frequency shift.  This allows the capacitance to be set for the desired frequency.

The CAN Standard's clock tolerance specifications are related to the CAN or CAN FD bit timing parameters used.  Generally the frequency shift created by only using a larger capacitance does not violate the clock tolerance specifications for most applications and therefore should be an acceptable solution.

I would say however, the series resistor approach is generally the preferred solution if there is a series resistor located between the OSC1 pin and the crystal as an option.  The exact value may need to be determined but most applications use a resistance of 100 ohms or less and it will depend on the crystal's internal motional parameters and the amount of capacitance used on the board as well. 

But generally we have found that you get similar results in terms of increasing the OSC2 min voltage level when using 20-50 ohms of series resistance as compared to increasing the load capacitance by 6pF.

Regards,

Jonathan