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DP83825I: Clock Availability at Power Ramp

Hamza Atifi
Prodigy 50 points
Part Number: DP83825I

Tool/software:

We ran into an issue with the power-up sequence of the PHY DP83825I. In the Rev. B of the datasheet at “Figure 5-1. Power-Up- Timing” there is  the information added: “Clock shall be available at Power Ramp. If not, hold RESET_N low and release it at least 100us after clock is stable.”

Investigations led to the assumption that our implementation of the PHY violates this obligation:

Firstly, we measured if XI is available at power ramp of VAVDD:

This picture shows the reset sequence of our SOM. VDD3V3A is connected to VAVDD and RMII_REF_CLK is connected to XI. As it can be seen the clock is not available at power ramp.

Secondly, we measured when the clock is stable in relation to our global reset-signal:

As it can be seen X_nRESET_OUT which is connected to RESET_N is not held low at least 100us after the clock is stable. RESET_N is controlled by a PMIC on our SOM, so the signal can’t be held down until the clock started because the clock is provided by the processor and the processor if affected by the reset-signal.

So the question is which problems can be caused by our implementation and if an additional software reset by MDIO-interface would be needed.

  • 0
    TI__Mastermind 39855 points

    Hello,

    This guidance in our datasheet is best practice for PHY initialization. If clock is not available at powerup and PHY is not held in reset, this could cause PHY to initialize in unknown state. Are you seeing any application issues in your validation efforts?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 50 points

    Hello Gerome,

    Thank you for your response,

    Currently, we haven't observed any application issues during our validation efforts, but we want to ensure the design's robustness by addressing this potential violation of the power-up sequence requirements.

    We would like to understand the potential risks. Specifically:

    1. Are there additional diagnostic checks or status registers we should monitor to confirm proper PHY initialisation?
    2. Would performing a software reset via the MDIO interface after power-up effectively mitigate this risk?

    We would appreciate your insight on how best to address this issue to ensure long term stability.

    Best regards,

    Hamza

  • 0 in reply to Hamza Atifi
    TI__Mastermind 39855 points

    Hello,

    Performing a pin reset at the earliest possible moment would be an effective way to mitigate if clock and reset assertion is not available immediately. Please note that this would cause device to re-strap so ensure that the strap lines are not driven at this point in time to avoid a mis-strap.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 50 points

    Hello,

    We would like to clarify two points regarding the reset:

    In our current design, the RST_N pin is connected to a global RESET signal, so a pin reset would require a redesign. Could you confirm if a pin reset is absolutely necessary or if there are alternative ways to ensure proper initialisation without modifying the hardware?

    Regarding a software reset, would issuing a reset via the MDIO interface after power-up be a viable alternative to mitigate any potential initialisation issues?

    Best regards,

    Hamza

  • 0 in reply to Hamza Atifi
    TI__Mastermind 39855 points

    Hi Hamza,

    SW reset would be a decent workaround, but the concern would be if the PHY is never properly initialized, the SMI has a possibility to not come up, thereby limiting this viability. So long in your evaluation this register lockup has not occurred, this SW Reset would be safe to move forward with.

    Sincerely,

    Gerome