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DS90UB927Q-Q1: NACK during Reset register 0x01 write (enabling Remote Auto Power Down)

Alexander Sverdlin
Prodigy 60 points
Part Number: DS90UB927Q-Q1

Tool/software:

Dear TI spcialist!

Could you please clarify the intended behaviour of the Remote Auto Power Down mode?

I've noticed (though not mentioned in datasheet?) that when Remote Auto Power Down engages (no FPD III Link detected), device is not accessible over I2C and all registers are in PoR state after it detects the link and comes up (even after Remote Auto Power Down bit is deasserted in Reset register 0x01). While not documented, this behaviour is reproducible and can be worked around.

The issue I have currently and it's rather sporadic is that asserting bit 7 (Remote Auto Power Down) in Reset register 0x01 sometimes is successful, but in many cases results in NACK on I2C bus if there is no FPD III Link at the time of write operation. No registers can be accessed after this write operation until FPD III Link is established.

My question is: shall this NACK be ignored? Does the serializer maybe enter sleep mode so early that it cannot even ACK this very write cycle setting it into Remote Auto Power Down mode?

Is there any way to know this specific write has been successful and it's not a problem with signal quality on the I2C bus?

Best regards,

Alexander Sverdlin.

  • 0
    TI__Genius 11870 points

    HI Alexander,

    The Remote Auto Power Down Mode is described in more detail in this section. 

    Alexander Sverdlin said:
    While not documented, this behaviour is reproducible and can be worked around.

    What is the workaround that you came up with?

    It is expected that there is no I2C communication to the SER when Remote Auto Power Down mode is enabled and the FPD-Link is disconnected, as it goes into "sleep mode." However, once the FPD-Link is connected again, you should be able to communicate with the SER. If you assert the bit while the FPD-Link is disconnected, the SER will immediately go into "sleep mode" and only stay in "sleep mode" until the FPD-Link is connected again. Is this the behavior you observed?

    Alexander Sverdlin said:
    My question is: shall this NACK be ignored? Does the serializer maybe enter sleep mode so early that it cannot even ACK this very write cycle setting it into Remote Auto Power Down mode?

    When you enable the Remote Auto Power Down mode, as soon as you disconnect the FPD-Link cable, the serializer goes into sleep mode. Sleep mode means that you cannot have I2C communication with the SER anymore, so the NACK is expected. 

    BR,

    Esther

  • 0 in reply to Esther Chang
    Prodigy 60 points

    Thank you for the quick reply Esther!
    My concern is that this very write to enable Remote Auto Power Down ends up with NACK quite often, not a consequent I2C access.

    So the internal I2C slave in the serializer doesn't even finish the transaction by the time it goes to sleep.

  • 0 in reply to Esther Chang
    Prodigy 60 points

    Regarding the documented behaviour... Well, it can be summarised as "To resume normal operation, the Remote Auto Power Down feature must be disabled", but the datasheet doesn't mention that all the registers are being reset to their PoR value. I even doubt that one really has to clear reg_0x01[7], as the chip is being fully reset anyway. So the behaviour observed is not really in line with the datasheet.

  • +1 in reply to Alexander Sverdlin
    TI__Genius 11870 points

    Hi Alexander,

    Alexander Sverdlin said:
    So the internal I2C slave in the serializer doesn't even finish the transaction by the time it goes to sleep.

    Yes, that is correct. 

    You are correct that when this bit is set, after every time the FPD-Link is disconnected and reconnected again, the register values will go back to their default value, whereas in normal operation, the register values will remain what you programmed it to be regardless of the FPD-Link state. 

    Therefore, to resume normal operation, this bit needs to be disabled, since it will continue to return the registers to their default value every time the FPD-Link is disconnected and reconnected again. 

    You still need to set reg_0x01[7] = 0 for normal operation, since after the FPD-Link is reconnected, this bit is not impacted by the "sleep mode" and remains at 1 until you set it to 0. 

    I understand this is a point of confusion in the datasheet, and will make it a note to update the description. Thanks!

    BR,

    Esther