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SN65DSI85: I am trying to connect 20.3" dual LVDS (3840 x 720) using SN65DSI85. At this time, I would like to inquire about the number of dsi mipi lanes.

huh myoung koo
Prodigy 20 points
Part Number: SN65DSI85
Other Parts Discussed in Thread: SN65DSI84

Tool/software:

I'm trying to connect 20.3" dual lvds lcd using SN65DSI85, so I have 2 questions.
First, we will connect DSI mipi to 2ea in CM4 (Orange Pi Compute Module 4), and please review whether it is possible to drive 20.3" LCD when connecting 4lane 1ea and 2lane 1ea as shown below.


Secondly, I would like to ask you to review whether it is possible to drive 20.3" LCD when connecting 2lane 1ea and 2lane 1ea, but connecting 2lane 1ea.
Attached is a 20.3" LCD data sheet.

C203RAT01.0_Ver1.0_20200721_202410311751.pdf

  • 0
    TI__Mastermind 23990 points

    Hello,

    When the DSI85 is configured for dual DSI channels, it supports ODD/EVEN or LEFT/RIGHT configurations. 

    On the other E2E thread I shared how you need more data lanes, and using the DSI85 to support this resolution:

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1488032/sn65dsi84-i-m-trying-to-connect-a-20-3-lcd-3840-x-720-using-sn65dsi84-at-this-time-can-the-dsi-mipi-run-20-3-lcd-3840-x-720-with-4lane-1ea-in-cm4

    Also, from the operating modes table you will see that for the "Dual DSI Input (Odd/Even) to Dual-Link LVDS" mode, DSI Channel A and DSI Channel B must have same DSI clock rate, same number of data lanes, and same data format. 







    Therefore, it's a valid use-case to use DSI channel A and B with 2 data lanes each. However, for your case, you would need more data lanes on each channel to support the resolution. And using 4 data lanes on ChA and 2 data lanes on ChB is not valid for Dual DSI input mode.

    Please use the DSI85 with dual-channel DSI and 3 or 4 data lanes each to support this resolution. 

    Please check the datasheet "7.4.6 DSI Lane Merging" section, SN65DSI8x resolution FAQ, and your E2E post about the resolution bandwidth.


    Best regards,
    Ikram



  • 0 in reply to Ikram Haque
    Prodigy 20 points

    Thank you for your response, Ikram Haque.


    In our current board configuration, the 'Orange Pi CM4' board uses an off-the-shelf board. Unfortunately, the 'Orange Pi CM4' board supports dual mipi, but only 4lane x 1ea and 2lane x 1ea.


    However, our solution is a solution that only displays fine dust and temperature on the picture screen, not on the video through 20.3" dual LVDS, so you can use only 18bpp, not 24bpp.


    When you said you use 18bpp, I would like to ask if it is okay to use mipi as below. If it is possible, I would like to use SN65DSI85.
    - case 1 : mipi 4lane + mipi 2lane
    - case 2 : mipi 2lane + mipi 2lane

    Please answer me.

    Best regards

  • 0 in reply to huh myoung koo
    TI__Mastermind 23990 points

    Hello,

    For dual-DSI application, both ChA and ChB should have same number of data lanes. So, you can't use "case 1 : mipi 4lane + mipi 2lane" 

    "- case 2 : mipi 2lane + mipi 2lane" or using 4 lane single DSI channel could be used if bandwidth allows.

    Part selection factors:

    1. LVDS clock range
    2. DSI clock range


    Calculate

    1. Using DSI84/85 LVDS CLK = (Htotal * Vtotal * frame_rate) / 2

                                                    = (4000 * 741 * 60) /2
                                                    = 88.92 MHz

    2. With 18 bpp,

    Using SN65DSI84, with 4 DSI data lanes

    DSI_CLK = (2 * LVDS_CLK * bpp)/(2 * number_of_DSI_lanes)
                    = (2 * 88.82 MHz * 18)/(2 * 4)
                    = 400.14 MHz, which is not within the 500 MHz DSI clock limit for the SN65DSI84




    However, using the SN65DSI85 with 8 data lanes,

    DSI_CLK = (2 * LVDS_CLK * bpp)/(2 * number_of_DSI_lanes)
                    = (2 * 88.82 MHz * 18)/(2 * 8)
                    = 200.07 MHz, which is not within the 500 MHz limit for the SN65DSI85

    Therefore, with 18 bpp application with this resolution, you can use:

    1. SN65DSI84 with 4 lanes

    2. SN65DSI85 with - 8 lanes (using all DSI lanes),
                                   - 4 lanes (2 data lanes on each channel ChA and ChB)
                                   - 6 lanes (3 data lanes on each channel ChA and ChB)

    Best regards,
    Ikram