DP83869EVM: Regarding DP83869HM

If I do this "pin 22 high, pin 36 low, and pin 35 low" without changing anything via registers, will it work in RGMII to 1000Base-X mode?

Hi,

That will configure the DP83869 for RGMII to 1000Base-X mode via pin straps. You should make sure all PHY strap settings are set as-needed. Another strap setting of interest is the fiber auto-negotiation enable strap in the datasheet:

If you need a specific PHY address, that can be set via pin straps too.

For most applications our PHYs can be configured entirely through pin straps without the need for register changes. If you'd rather use register access to configure the PHY, you can use the following steps described in the datasheet: 

Best,

Shane

I have Dp83869EVM board with me. I have tested above what you said it didn't work.

I made pin 22 High, basically shorting the OP_MD[0]
pin 35 & 36 Low - OP_MD[1] & OP_MD[2] set to as open circuit.

• • Pin 22 → HIGH - basically shorting the OP_MD[0]
  • Pin 36 → LOW -  OP_MD[1] set to as open circuit.
  • Pin 35 → LOW  - OP_MD[2] set to as open circuit.
  • Pin 47 → LOW (Auto-negotiation enabled) - set LED0 strap towards GND
  • Pin 46 → HIGH (Configure pin 24 as Signal Detect) - set LED1 strap towards AUX_IOVDD

  I have connected all the RGMII to logic analyzer to see if I can do a ping test from my laptop, but no signals were detected.
  
  Setup: PC -- UMC-GA1f1T(SFP1G-SX-85 in it) -- DP83869EVM (SFP1G-SX-85 in it) -- RGMII—Logic Analyzer.

  • = Data -- (Electrical to Fiber) -- (Fiber to RGMII) - Logic Analyzer

Hi,

I have a few comments on the setup:

Fnu Premsagar said:

I made pin 22 High, basically shorting the OP_MD[0]
pin 35 & 36 Low - OP_MD[1] & OP_MD[2] set to as open circuit.

1. OP_MD[0] should be pulled high with a 2.49K resistor, OP_MD[1] and OP_MD[2] should be pulled low with a 2.49K resistor. Can you measure the voltage on these straps to check that they fall within the Vmin/Vmax for their respective setting?

2. I see in your first picture that LED_0 is lit. This implies that the link is stable between the DP83869 and its MDI link partner. In your second image, LED_0 is off. What change was made between these two images?

3. From this E2E, there are signal integrity concerns with evaluating the RGMII interface on this EVM. Routing a high speed signal between boards using jumper wires can negatively impact the signal. It would be good to probe the RGMII interface to ensure VIH/VIL/Setup/Hold times are being met.

Best,

Shane

Hi,

Please ignore the 2nd image where the LED0 is off; I connected the fiber TxRx pins in a reverse way, so that's the reason the LED0 was off; the 1st one is correct. I have updated the above reply (removed the wrong image uploaded).

Currently, if I power up the board, only LED0 is on.

I have measured the voltage; I see almost 3.3V between OP_MD[1] strap pins, and 0V across OP_MD[2]. At OP_MD[0], if I don't short it, I measure 3.3V.

Fnu Premsagar said:

Please ignore the 2nd image where the LED0 is off; I connected the fiber TxRx pins in a reverse way, so that's the reason the LED0 was off; the 1st one is correct. I have updated the above reply (removed the wrong image uploaded).

It sounds like the MDI Fiber connection is good, but there may be an issue with the RGMII side or PHY configuration

1. If you are seeing almost 3.3V on OP_MD[0], what voltage is at VDDIO? OP_MD[0] needs to be at most 0.88 x VDDIO per the datasheet table I showed above.

2. To rule out strapping concerns, are you able to write the registers in section 7.4.8.2 of the datasheet? This would configure the PHY to RGMII - Gigabit Fiber:

Best,

Shane