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TCAN1462-Q1: CAN FD Topology Design with SIC

Zhihong Lin1
Prodigy 60 points
Part Number: TCAN1462-Q1

Tool/software:

Hi TI CAN Expert,

Currently I am considering the worst CAN topology using TCAN1462-Q1 (with SIC) like below:

  • CAN FD frame
  • One master #0 connected with 6 branches in parallel
  • Each branch has 6 CAN node (#1~#6, each branch can be considered as linear topology)
  • Each branch max total distance from #0 to #6 is 20 meters
  • Typical data rate: 2Mbps (max to support 5Mbps if possible)
  • The communication only happen from #0 to #1-#6, or from #1-#6 to #0. One branch won't talk to other branch. 

Physical connection:

  • For #0, there are 6 connectors for cable, and each connector is connected in parallel to CANH/CANL. There is no gateway there, only one CAN transceiver with termination. 
  • For #1-#6, there are 2 connectors for cable, and each connector is connected in parallel to CANH/CANL

My questions:

  • Does this topology make sense to you? And for this topology, how to design the termination network?
  • Does TI has any tool to simulate the topology and any way to improve it?

Looking forward to your feedback!

Regards

Nic

  • 0
    TI__Guru 51106 points

    Hi Nic,

    • Please note that the standard recommendation is a linear bus with two 120 ohms terminations at the extreme ends similar to figure 9-3 of the data sheet (especially at higher speeds up to 5 Mbps). However, the star topology can be made to work with SIC devices such as the TCAN1462-Q1.
      • I would recommend max data rate at 2 Mbps instead and reduced total lengths as achieving 5 Mbps on a 6 way star topology with 20 m stubs is much more challenging and would require some experimentation. Ensure each drop from main node #0 to the transceiver pin is kept as short as possible. Do not add extra cable loops near #0.
      • I would recommend to terminate node 0 similar to figure 9-2 of the data sheet (preferably split termination)
      • Also, terminate each #6 branch with a higher resistor (240 to 720 ohms) so that all branches are connected in parallel with total bus load around 60 ohms.
        • For example, if 120 ohms is used at #0 with each of the 6 branches using 720 ohms at the far end, this yields one 120 ohms with six 720 ohms all in parallel - which is close to 60 ohms as the total bus impedance. Exact values will vary based on EMC needs, bus length, etc.
    • You may use IBIS models to get an idea of reflections, ringing, rise/fall times.

    See Controller Area Network Physical Layer Requirements  or more information, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 60 points

    Thanks Michael!

    Looks like your comment is positive that this topology will work for 2Mbps. 

    For "Ensure each drop from main node #0 to the transceiver pin is kept as short as possible", could you be more specific about the distance from where to where? Not clear to me here. 

    This one?

    Or this one?

    "Do not add extra cable loops near #0." Do you mean that don't add more branches to #0, 6 branches is already too much. 

    Regarding IBIS model, does TAN1462-Q1 has IBIS model, and do you have a guide document for me to do the simulation? thanks.

    Regards

    Nic

  • 0 in reply to Zhihong Lin1
    Prodigy 60 points

    One more question:

    "Exact values will vary based on EMC needs, bus length, etc."

    Any guideline about termination value vs EMC/bus length?

  • +1 in reply to Zhihong Lin1
    TI__Guru 51106 points

    Hi  Nic,

    1. Yes, the 2nd one. I.e., the wiring from the pin on the PCB or within the node to the connector that attaches the bus, thereby minimizing the distance between the transceiver output and the point where it connects to the main bus.

    2. I meant, do not add any unnecessary loops or cable lengths. Each branch's connection point is as direct as possible, i.e., extra loop or bend can degrade signal quality.

    3. Unfortunately, I do not see any SIC IBIS models as of this time and would recommend any 8 pin IBIS model for reference.

    4. Total bus impedance of 60 ohms for optimal performance, split termination for optimal EMC, shorter lengths / stubs for less for optimal EMC and easier for matching desired impedance I.e., longer wiring loops will require additional tuning of termination resistor values. Please refer to Controller Area Network Physical Layer Requirements  for more information, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 60 points

    Hi Michael,

    I am using TCAN1462-Q1 to do the topology waveform measurement. Below is the setup. Termination is followed by your suggestion. 

    Slave #4 (orange) is sending message to master#0 (orange). The message is 5 dominant followed by 1 recessive.

    Below is the measured waveform. Blue is Slave #4 TXD, red is master#0 RXD. Yellow is CANH and green is CANL at master#0.White is the differential signal of CANH-CANL.

    I record 1Mbps/3Mbps/5Mbps waveform. When data rate goes up, I don't see more ringing. However, the CANH falling time and CANL rising time becomes longer. For 5Mbps, during recessive bit, CANH and CANL don't even go to 2.5V anymore. Do you know any reason for this? Looks like it is not caused by reflection. Is it caused by more capacitance from cables?

    1Mbps

    3Mbps

    5Mbps

  • 0 in reply to Zhihong Lin1
    Prodigy 60 points

    Hi Michael,

    I am using TCAN1462-Q1 to do the topology waveform measurement. Below is the setup. Termination is followed by your suggestion. 

    Slave #4 (orange) is sending message to master#0 (orange). The message is 5 dominant followed by 1 recessive.

    Below is the measured waveform. Blue is Slave #4 TXD, red is master#0 RXD. Yellow is CANH and green is CANL at master#0.White is the differential signal of CANH-CANL.

    I record 1Mbps/3Mbps/5Mbps waveform. When data rate goes up, I don't see more ringing. However, the CANH falling time and CANL rising time becomes longer. For 5Mbps, during recessive bit, CANH and CANL don't even go to 2.5V anymore. Do you know any reason for this? Looks like it is not caused by reflection. Is it caused by more capacitance from cables?

    1Mbps

    3Mbps

    5Mbps

  • 0 in reply to Zhihong Lin1
    Prodigy 60 points

    To further investigate this, I am doing more measurement. All is done at 5Mbps. 

    Case-1: A to talking to B through 1m cable. the waveform is perfect.

    Case-2: Add C through 10 cable to case-1. The waveform becomes worse than case-1.

    Case-3: Remove C, only leave 10m cable there. The waveform is worse than case-2. 

    Case-4: Add 3 more cables to case-3, without adding CAN node, only cables. The waveform is worst. And you can see, CANH and CANL don't even go to 2.5V anymore. (Similar like the above topology measurement)

    I wonder if this is caused by larger RC in the network? Looks like it is not caused by mismatch/ reflection. Do you have any suggestion how to resolve this?

    Compare case-2 and case-3, C is same, while R in case-2 is smaller than case-3. So case-3 is worse. 

    Compare case-3 and case-4. R is same, while C in case-4 is larger than case-3. So case-4 is worse. 

  • 0 in reply to Zhihong Lin1
    TI__Guru 51106 points

    Hi Zhihong, 

    Thanks for the detailed information as your analysis is spot on. I.e., as C increases or R becomes significant, RC time constant increases for degradation.

    Please note that you are correct to suspect capacitive loading for the signal degradation at higher speeds as SIC helps reduce reflections but not capacitive effects. I.e, as speed increases, the ability to charge / discharge larger cap in time for a clean bit can become a challenge as the bus cannot settle in time, leaving voltages closer to dominant levels for the reduced differential voltage observed.

    I would recommend sticking with the 2 Mbps or lower with this topology, especially with no concerns for ringing, rather than than the slow transitions.

    Note that case 2 includes the added node compared to case 3. This reduces effective R for a faster charge / discharge as case 3 includes a larger R for worse RC observed as degradations.

    • You may further reduce stub lengths to reduce C (and avoid dangling stubs with no terminations as floating open cables adds C).
    • Consider using split termination at node 0.
    • You may tune and adjust termination resistors at the far ends to control the signal levels. Observe the manageable tradeoffs for signal integrity and voltage levels with higher and lower resistors as this helps adjust  RC delay.
    • May further consider intelligent switches to enable / disable nodes to manage capacitive load dynamically, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 60 points

    Quick question here:  why does "Consider using split termination at node 0" help here? Doesn't it help on EMC?

  • 0 in reply to Zhihong Lin1
    TI__Guru 51106 points

    Hi Zhihong,

    Yes, for an improved stability setting a defined common mode voltage across the bus to help maintain better thresholds at startup or during transients, thanks.

    Best Regards,

    Michael.

  • 0 in reply to Michael Ikwuyum
    Prodigy 60 points

    Hi Michael,

    In CiA601-3, the worst case phase margin is given as below. However, it is based on only data phase. Can the worst case in data phase cover the worst case in arbitration phase as well？

     

    My opinion is that the worst case PM in data phase cannot cover the worst case PM in arbitration phase. For arbitration phase, if the BUS length is long, then you have to set large prop_seq to compensate the propagation delay for loop-back sampling, which means the phase margin is small, and can be even smaller than above equation. 

    Is my understanding correct?

    Regards

    Nic

  • 0 in reply to Zhihong Lin1
    TI__Guru 51106 points

    Hi Nic,

    Yes, your understanding is correct as the data phase is not as worse comparing to the arbitration phase which includes the longest prop delay (especially for long buses and star topologies). Hence, worst case loop delay + prop_seq timing needs to be considered for arbitration to account for the larger prop sequence thereby resulting to a smaller phase margin in arbitration, thanks.

    Best Regards,

    Michael.