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TCA9617B: Pedestal Overshoot in TCA9617B

Conor
Guru 12235 points
Other Parts Discussed in Thread: TCA9617B, TINA-TI

Hi,

We are currently designing with the TCA9617B and would like to clarify some points regarding Section 7.2.1.2 Detailed Design Procedure in the datasheet, specifically concerning pedestal overshoot. Could you kindly provide your insights on the following questions?

Question 1
If the input signal to the B-side is a clock with a 50% duty cycle, I believe that an increase in pedestal overshoot could distort the duty cycle of the output waveform from the A-side. Is this understanding correct?

Question 2
To prevent pedestal overshoot from occurring, how much should the input signal to the B-side be rounded?
Alternatively, are there any other methods to prevent pedestal overshoot?

Question 3
Does pedestal overshoot pose a problem for the TCA9617B in normal operation?

Question 4
Is it possible to perform a signal integrity simulation of the TCA9617B using TINA-TI? Can pedestal overshoot be reproduced?
If so, could you provide some reference data?

Question 5
Is it possible to perform a signal integrity simulation using the IBIS model of the TCA9617B with an SI simulator other than TINA-TI?
Can pedestal overshoot be reproduced in such a simulation?

Thanks,

Conor

  • 0
    TI__Mastermind 48308 points

    Hi Conor,

    Conor said:
    Question 1
    If the input signal to the B-side is a clock with a 50% duty cycle, I believe that an increase in pedestal overshoot could distort the duty cycle of the output waveform from the A-side. Is this understanding correct?

    I am assuming this clock waveform is open-drain correct? 

    The pedestal overshoot is a result of fast rise-times <20 ns. The shorter the rise-time, the worst the pedestal overshoot. If using a PU resistor within the IOL characteristics of the datasheet, I suspect that the pedestal overshoot shouldn't be a problem with a 50% duty cycle signal. The A-side output is created from the B-side input. So the duty cycle shouldn't change much from B-side to A-side. 

    Conor said:
    Question 2
    To prevent pedestal overshoot from occurring, how much should the input signal to the B-side be rounded?
    Alternatively, are there any other methods to prevent pedestal overshoot?

    As long as the rise time is greater than 20ns, the pedestal overshoot shouldn't be a worry. 

    Conor said:
    Question 3
    Does pedestal overshoot pose a problem for the TCA9617B in normal operation?

    I have not run into the pedestal causing an issue for the customer. 

    PU resistors are usually sized with rise-times much > 20 ns. 

    Conor said:
    Question 4
    Is it possible to perform a signal integrity simulation of the TCA9617B using TINA-TI? Can pedestal overshoot be reproduced?
    If so, could you provide some reference data?

    No PSPICE model for this device. 

    Conor said:
    Question 5
    Is it possible to perform a signal integrity simulation using the IBIS model of the TCA9617B with an SI simulator other than TINA-TI?
    Can pedestal overshoot be reproduced in such a simulation?

    I simulated using the following schematic and TCA9617B IBIS model. However, it looks like the IBIS does not model the pedestal or static voltage offset output correctly. 

    Regards,

    Tyler