• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 112 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS96F175MQML-SP: Relative timing delays

Michael Bolt46
Prodigy 90 points
Part Number: DS96F175MQML-SP

Tool/software:

I am using an RS485 bus with data and clock at 5 Mbps.

I need to perform a worst-case analysis on the timing, to verify the margin between data and clock.

Do you have any data on the relative timing delays of 2 receivers in the same package?

Or can I assume half the worse-case delay as the difference between receivers, given that they're on the same process and at the same temperature?

Many thanks,

Michael

  • 0
    TI__Guru 73971 points

    Hi Michael,

    Michael Bolt46 said:

    Do you have any data on the relative timing delays of 2 receivers in the same package?

    Or can I assume half the worse-case delay as the difference between receivers, given that they're on the same process and at the same temperature?

    This is probably a safe assumption. Generally the skew between two channels will be minimal when they are on the same die, at the same temperature, with the same process (so process variation wouldn't effect it much). I wouldn't expect a very large skew difference and half of the worse case delay would probably give a lot of margin for you. 

    -Bobby