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TCA9617B: Understanding Inverted Pedestal on the SOV side of I2C Buffer

Kiran S
Prodigy 10 points
Part Number: TCA9617B
Other Parts Discussed in Thread: TCA9517A, TCA9517

Tool/software:

Under Section 6.3, 

Analyzing the  waveform of I2C bus on the B side, Things I can comprehend is -

1. Since ACK is done by B side (Vol of Target) so in this case A is Master sending the data to slave, B. 

2. Blue Marked area in the circle, device on B releasing the data line and since the Buffer output is still ON the B stays on at SOV. once the Signal at the A rises above 0.3 of VCCA  buffer turns OFF and the B line charges to VCCB. 

Thing I am not able to understand is the inverted Pedestal, my thinking is like -

 Device on B being the receiver which only reads the bus, until the 9th cycle it doesn't change anything on the bus  and the Device on the A is Tx'er. When A goes low, Buffered output low is generated on B side which should be ~0.5V (SOV), Why does it go to 0V and then goes back to SOV level.

I also  see the below image, which depicts the signal - A driving the B , Here I don't see B-side going to 0V and then moving to the offset voltage, which further confuses me.

Kindly Help me know what am I missing, explaining the logic behind that 0.

Regards, 

Kiran 

  • 0
    Guru 316690 points

    The datasheet says that "the A side falling below 30% of VCCA turns on the corresponding B-side driver and drives the B-side down momentarily to 0V before settling to approximately 0.5V."

    Figure 6-3 does not show this because it is concerned only about the timing of the edges.

  • 0 in reply to Clemens Ladisch
    Prodigy 10 points

    Hi Clemens, 

    Thanks for replying, yes I have read that statement about the momentary 0V before reaching to 0.5V. My ask was for why does it reach to 0V ? anything like related to the pull up resistor value,  fast fall time, Transient behavior of zener prior settling to 0.5V ? 

    As I except  the waveforms to look like fig. 6.3

    Regards,

     Kiran

  • 0 in reply to Kiran S
    Guru 316690 points

    The B-side output uses an offset of about 0.5 V to be able to detect other devices also pulling the line low. Apparently, the voltage regulation has some undershoot.

  • 0 in reply to Kiran S
    TI__Mastermind 47328 points

    Hi Kiran,

    The reason the buffer drives to 0V and then settles to 0.5V is by design. I believe it was simpler to design circuitry to drive strongly to GND and then release to a static voltage offset (0.52V) than it was to drive strongly to a 0.52V from VCC. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 10 points

    Thanks Clemens and Tyler. 

    Tyler,  Then in the application note - SCPA054, Zener diode is just used for representation of static voltage offset (0.5V) and not the actual used in the circuit.

    Regards, 

    Kiran 

  • +1 in reply to Kiran S
    TI__Mastermind 47328 points

    Hi Kiran,

    I think for some of our buffers like TCA9517 / TCA9517A it may use this type of architecture because if I recall correctly, 9517 drives to the static voltage offset. 

    In order to have faster fall times, 9617B falls to GND then settles at the SVO, so it is different output architecture than the 9517. 

    VOL on B-side for the TCA9517:

    You can see that SDA is driven to the static voltage offset ~0.52V, not GND in this case for the 9517. 

    Regards,

    Tyler