Tool/software:
Team,
I would like to ask few questions about the TIOS102x chip specifications.
From the datasheet:-
“The VCC and OUT pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC 61000-4-5 surge with a source impedance of 500 Ω.”
This statement is same as TIOS101x existing chip using.
During +1kV Surge test apply on OUT pin, the questions are:
1. What’s the behavior on the chip
Does it enter Current Fault Detection mode & NFAULT output Indication?
2. If Yes, does it follow the timing switching characteristics as shown below?
It means OUT pin need to wait for “NFAULT driver re-enable wait time + max. of OUT re-enable delay after UVLO” timing, total needs about 65ms to recover the output?
3. Is there any solution that it won’t enter Current Fault Detection mode & NFAULT output Indication during +1kV Surge test?
4. Is there any TI testing report for this Surge test?
Thanks,
Frank
If have any difficulties to answer it, then kindly let me know later
