• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 98 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB913A-Q1: FPD-Link III interface

Hiroshi Murofushi
Prodigy 10 points
Part Number: DS90UB913A-Q1

Tool/software:

Hello

I am designing a circuit using a serializer (DS90UB913A) and a deserializer (DS90UB914A). 

I am inputting a 27MHz PCLK, data, and synchronization signal to the serializer side.

However, the PCLK output from the deserializer is 13.5MHz, and the synchronization signal is similar to the data and is different.

What do you think is the cause?

Please advise.

  • 0
    TI__Mastermind 26810 points

    Hello,

    Thank you for reaching out. Are you talking about the imager's PCLK? Is the imager's PCLK being used as the device's reference clock or is an external clock being fed to the device? What mode are you operating in? A 27MHz PCLK is on the lower end of supported frequencies, and the devices would need to be operating in 12bit LF mode. Can you explain what you mean by the synchronization signal being similar to the data? If possible, screenshots or images of the signals would be helpful.