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DP83869HM: 1000BASE-T MDI inter-pair skew

Marek Havelka
Prodigy 20 points
Part Number: DP83869HM

Tool/software:

Dear TI team, 

we are currently implementing 1000BASE-T with DP83869HM PHY and I have question regarding the inter-pair skew on PCB. I found multiple answers from multiple sources and I would like to have deeper understanding of this problem. 

Values which I found: 

Nvidia specifies 0.25 mm of interpair skew in their Jetson Orin NX product design guide. 

WE specifies 330 ps (50 mm on PCB) in their 1000BASE-T reference design and refers to 802.3. However, 802.3 does not provide this information. This is also case of the Gigabit Ethernet 101: Basics to Implementation on altium website. 

802.3 specifies is the inter-pair skew for the whole 1000BASE-T system which is 50 ns (worst inter-pair skew on 100m of CAT5e cable). 

I also found that during the autonegotiation between PHYs there is a training sequence which help PHYs identify polarity, crossing and skew between individual pairs. I would guess that there is a register in PHY that stores this information but I haven't found it in DP83869HM datasheet. 

My question is - what is the mechanism that PHY uses to compensate the inter-pair skews and what is the maximum inter-pair skew that the PHY can correct? Based on the 802.3 standard I would guess that it is 50 ns (from standard) + environmental conditions: 10 ns (also from standard) + some margin. But I don't have any proof for this. 

Thanks for your help, 

Marek 

Here are the resources: 

https://resources.altium.com/p/gigabit-ethernet-101-basics-implementation

https://www.we-online.com/components/media/o721295v410%20RD016a%20EN.pdf

  • 0
    TI__Genius 12171 points

    Hi Marek, 

    Our PHYs are able to work with skews within our recommendation of 20 mils of trace-length difference in the PCB layout. Please refer to this application note. 


    For the time-delay skew introduced by the cable, PHY can work with maximum skew of under 50 ns. If the cable causes more skew than 50 ns, PHY will not be able to establish the link.

    The PHY deals with the skew from the cable via elastic buffer in the CDR process. Based on the faster-arriving packet, the CDR block will add additional delay in the buffer to wait for the delayed packet and process the packet altogether once all the packet from the different pairs arrive. 

    In our PHYs, we look at the SFD (Start of Frame Detect) Variation at RX channel and adjust the buffer to match the cable's time delay skew. 

    Please refer to the DP83869HM datasheet section 7.3.2 for more detailed information. 

    Resources:
    https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/transmit-elastic-buffer.html

    Please let me know if you have any other questions. 

    Best,
    J