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TCA9539-Q1: reset for timeout

Ryan Wang
Expert 7435 points
Part Number: TCA9539-Q1
Other Parts Discussed in Thread: TCA9538, , TCA9539

Tool/software:

Team,

What does below mean? timeout mean I2C timeout? What scenario it might be?

"system controller " mean customer MCU?

Does below mean TCA9538 will reset by itself when I2C timeout happen?

"The system controller can reset the TCA9539-Q1 in the event of a time-out or other improper operation by asserting a low in the RESET input." (From TCA9539 datasheet)

Customer found sometimes TCA9539 got reset (NO Output, all register return to default), when they short SCL to GND during normal I2C operation. (They mimic some abnormal case in the field ). (/RESET pin keeps HIGH)

Is above phenomenon expected? Why?

Thanks

  • 0
    Guru 316920 points

    Neither TI nor the I²C specification define timeouts. A timeout is a common error detection mechanism implemented in the host firmware.

    The TCA9539-Q1 will reset only when either /RESET goes low or when the supply voltage dips (see section 9.1). Shorting SCL to GND while another device is actively driving SCL high might cause the supply voltage to go down.

  • 0
    TI__Mastermind 47748 points

    Hi Ryan,

    Ryan Wang said:
    What does below mean? timeout mean I2C timeout? What scenario it might be?

    Timeout could be like an idle condition where SDA is held LOW by some device on the I2C bus. The bus "times out" because it is idle for a period of time. 

    Ryan Wang said:
    "system controller " mean customer MCU?

    System Controller = Host, MCU, SoC, the I2C master/controller device.

    Ryan Wang said:
    Does below mean TCA9538 will reset by itself when I2C timeout happen?

    No. TCA9538 needs external influence by the host controller for a RESET to happen. 

    Ryan Wang said:

    Customer found sometimes TCA9539 got reset (NO Output, all register return to default), when they short SCL to GND during normal I2C operation. (They mimic some abnormal case in the field ). (/RESET pin keeps HIGH)

    Is above phenomenon expected? Why?

    Thanks

    Can we confirm that /RESET is always HIGH on the oscilloscope during the SCL to GND condition? 

    What is the state of VCC? 

    Is the customer abiding by the glitch width, height, metrics in the datasheet to prevent a power reset? 

    Regards,

    Tyler