DS280BR820: ds280br820

typo in my previous request: the deep differences between ds280br820, tdp2044 and ds280br810

Hi Drew,

Thanks for your prompt reply. I appreciate.

So, as per my understanding, we have a better boost with DS280 than TDP2044 but the return loss is worst, means some piece of energy back to the Tx. I do not know how much it can impact the Sink (FPGA receiver). 4dB diff for the SDD11 (-16dB vs -12dB), means a lost of 40% I guess. The other strange thing is why the SDD11 and SDD22 are different for DS280. Each lane should be the same. I do not explain this difference.
I also seen that the ACCM is defined in DS280 but it isn't in TDP2044, same for rise time.
I can see some settings for the pre-post cursor in DS280, while nothing in TPD. This pre/post cursor should help to enable/tune some taps in the FFE if my understanding is correct. It seems that TDP2044 has only CTLE and not FFE but difficult to say. This FFE. These pre-post cursors should help to open the eye such like a better sampling on the incoming pulse, that should help the ISI.

Which product to choice remains difficult but both at stamped 20Gbps.

Regards

Rhani

Hi Rhani,

abdelhani menzer said:

The other strange thing is why the SDD11 and SDD22 are different for DS280. Each lane should be the same. I do not explain this difference.

SDD11 is receiver return loss.  SDD22 is transmitter return loss.

abdelhani menzer said:

I also seen that the ACCM is defined in DS280 but it isn't in TDP2044, same for rise time.

What is ACCM?

abdelhani menzer said:

I can see some settings for the pre-post cursor in DS280, while nothing in TPD. This pre/post cursor should help to enable/tune some taps in the FFE if my understanding is correct.

Please note that DS280BR8x0 has a linear and non-linear (limiting) mode.  The pre/post are only applied in the limiting mode and use a fixed delay (since the device has no awareness of the data rate of the signal).  The TDP2044 operates as a linear redriver.  Do you require a linear redriver?  You will need this if you use a protocol with link training.  If you don't use link training, a limiting redriver will work.

abdelhani menzer said:

Which product to choice remains difficult but both at stamped 20Gbps.

Can you share a block diagram for your project with estimated insertion losses?

Thanks,

Drew

Hi Drew,

Yes correct, SDD22 is for the Tx. I misread this.

ACCM is the common mode AC output: Tx for electrical interfaces is typically a fully differential circuit whose output should have constant common mode voltage. The causes of common mode AC signal in the TX are: the time skew (package, vias, traces for example) BW mismatch in the differential circuit or uncorrelated noise (common between pin drivers). It is expressed in mV. It is currently defined in TDP2044 but not in DS280. The impact causes some distortion of the differential signal and could impact the Sink. It can also cause some EMI.

Yes I'm using link training but I'm not sure to understand the correlation between link training and linear redriver. Why the limiting redriver cannot work with link training ?

The insertion losses at 10Ghz will be around -12dB and for some other projects @-5dB.

regards

Rhani

Hi Rhani,

What are the equalization capabilities of your FPGA?

abdelhani menzer said:

Yes I'm using link training but I'm not sure to understand the correlation between link training and linear redriver. Why the limiting redriver cannot work with link training ?

Link training forms a feedback loop between TX and RX to identify optimal TX settings.  The TX adjusts its settings (i.e. swing, pre, post) and the RX measures the signal quality and requests adjustments to the signal.

A limiting redriver breaks this feedback loop because adjustments to swing, pre, and post do not propagate through the redriver.

Thanks,

Drew