DS90UB927Q-Q1: About Dual LVDS transmission method

Ryu Yamashita

Part Number: DS90UB927Q-Q1
Other Parts Discussed in Thread: DS90UB947-Q1, DS90UB928Q

Tool/software:

Hi team,

I wanted to use DS90UB947-Q1 for Dual LVDS transmission, but I want to separate ODD and EVEN CLK.
Therefore, I want to use DS90UB927Q and DS90UB928Q together for Dual LVDS transmission.
Is this possible?

Best Regards,
Ryu.

over 1 year ago

0 Aaron Heng over 1 year ago

TI__Mastermind 43120 points

Hi Ryu-san,

Can you please help clarify the question? Are you saying that you would like to use 947 or 927 for your applications?

Aaron

0 Ryu Yamashita over 1 year ago in reply to Aaron Heng

Genius 5130 points

Hi Aaron,

Sorry.
I was going to use 947, but gave up because there was only one CLK.
So I am going to use 927, but I wanted to confirm if it supports Dual LVDS if I use two of them.

Best Regards,
Ryu.

0 Aaron Heng over 1 year ago in reply to Ryu Yamashita

TI__Mastermind 43120 points

Hi Ryu,

The 927 has only one OLDI input where 947 has dual port for OLDI, but still reference to the same one single clock input. Depending on your resolution, 927 can only support up to 720p.

Hope this helps. Let me know if you have additional questions.

Aaron

0 Ryu Yamashita over 1 year ago in reply to Aaron Heng

Genius 5130 points

Hi Aaron,

If it is up to 720p, does that mean it can be handled by using two 927s?
I know I can achieve this with a 947, but as I said before, I want to separate the CLKs.

Best Regards,
Ryu.

+1 Aaron Heng over 1 year ago in reply to Ryu Yamashita

TI__Mastermind 43120 points

HI Ryu-san,

You can run two 927s, but they are independent which mean it doesn't have the synchronization features. Is there a reason why you need to have two independent CLK when you are trying to send the video for example 1920x1080? Anyway, you need to provide me more additional information of your application? I can create a private room or you can reach out to your local TI FAE for assistance.

Aaron

0 Ryu Yamashita over 1 year ago in reply to Aaron Heng

Genius 5130 points

Hi Aaron,

Thank you very much.
I will review the specifications once again.
If I have any more questions, I will contact you in another thread.

Best Regards,
Ryu.

0 Ryu Yamashita over 1 year ago in reply to Ryu Yamashita

Genius 5130 points

Hi Aaron,

I'm sorry, but I'm just wondering if you can help me with one related point.
When receiving Dual LVDS with 947, how are the Odd and Even CLKs supposed to be input respectively?

Best Regards,
Ryu.

0 Aaron Heng over 1 year ago in reply to Ryu Yamashita

TI__Mastermind 43120 points

Hi Ryu,

The 947 receives the video from source as a passthrough. You may use the register 0x5B bit 3 to determine your even or odd as the primary or secondary link. You may see this example attached here.

1185.947_Validation_Odd_Even_on_FPD3.pdf

Aaron

0 Ryu Yamashita over 1 year ago in reply to Aaron Heng

Genius 5130 points

Hi Aaron,

I could not understand this document.
What I want to ask is how to handle Odd and Even CLKs.
For example, should I input Odd CLK to CLK+ and Even CLK to CLK-?

Best Regards,
Ryu.

0 Aaron Heng over 1 year ago in reply to Ryu Yamashita

TI__Mastermind 43120 points

Hi Ryu,

I don't think you would need to assign the old or even clock to the CLK+ or CLK-. These are coming from the source which is passthrough. The splitting or alternating should be done from the device side.

Aaron

0 Ryu Yamashita over 1 year ago in reply to Aaron Heng

Genius 5130 points

Hi Aaron,

We apologize.
I didn't quite understand.
I was thinking of a configuration like this, but what do you mean by not having to input CLK?
Also, is it possible to send PWM to GPIO as shown in the diagram?

Best Regards,
Ryu.

+1 Miguel Bolante over 1 year ago in reply to Ryu Yamashita

TI__Mastermind 24925 points

Hi Ryu,

To clarify Aaron's point, the 947 will only have one CLK input from the SoC, see below:

Data channels D0-D3 are channel 1 LVDS while D4-D7 is channel 2 LVDS.

Assuming you have Dual FPD-Link input to the DS90UB948, it will look like this for the EVEN/ODD assignment on the 948:

Corresponding to these pinouts on the 948:

CLK1 and CLK2 will operate at HALF the rate as the PCLK for each OLDI port, is there a specific requirement in your system need where the CLK1 needs to be different than CLK2?

If not, this is how both CLKs are handled from the OLDI output on 948, they should be half the PCLK (single CLK_IN from 947).

PWM signal is possible through the GPIOs between 947 and 948, please make sure they are matched (GPIO0 input from 947 corresponds to GPIO0 output on the 948 for example).

Best,

Miguel

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DS90UB927Q-Q1: About Dual LVDS transmission method