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SN65DSI86: Use DSI CLK vs. the Ref CLK

David (ASIC) Liu
Guru**** 182311 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: CDCEL913

Tool/software:

Hi,

We are currently considering using our own clock generator for the LVDS to eDP Bridge SN65DSI86.

What advantages and disadvantages would we have at this point? The question specifically aims at whether there are disadvantages if the clock is fed via the DACP/N lanes instead of refclock?

The CDCEL913 chip sits on the Evalboard, but it has 3 outputs and is programmable. These are features that we do not need for the standard version.

For an initial prototype setup: Can a simple 4 PIN oscillator be used here?

What is recommended for pages TI for refclock for a block?

  • 0
    TI__Guru**** 182311 points

    Hi,

    The clock source for the SN65DSI86 is derived from one of two sources: REFCLK pin or DACP/N pins. On the rising edge of EN, the sampled state of GPIO[3:1] as well as the detection of a clock on REFCLK pin is used to determine the clock source and the frequency of that clock. The DSI_CLK tends to have worse jitter performance than a reference clock. When using the DSI_CLK and depending on its jitter performance, it may impact the video performance. 

    On the DSI86 EVM, https://www.ti.com/lit/ug/sllu204/sllu204.pdf, we used a 27MHz crystal oscillator, the part number is ABM8-27.000MHZ- 10-1-U-T.

    Thanks

    David