DP83822I: DP83822

Hi Ed,

When the link communication error happens, do you notice the link drop on the MDI side of the PHY? This would be indicated by LED_0 going low, or reading bit 2 of register 0x0001:

If the link does not drop on the MDI side, it suggests an issue with the MAC (MII) interface. Can you show a block diagram of the system with the MAC/MII interface included?

Best,

Shane

Link sows UP through out.

Hi Shane,

Thank you for your response. I appreciate it. Link Status shows UP through out the event. Below is a decoded version of the register data: 

Thanks Ed,

I'd like to check the signal path between the PHY and the fiber module to rule out any implementation issues on this end. 

1. Can you probe the signal from the fiber module and show the eye diagram near the receiver of the PHY? These would be the RD_P/M pins

2. Which fiber module/connector part(s) are you using in this design? It would be good to see these for more context on your system. If you can share the schematic that would be ideal.

3. If you cannot provide the schematic, can you verify that your implementation follows the example in section 9.2.2 of the DP83822 datasheet? Here is that example for reference:

Best,

Shane

Also for item 1, it would be good to see the signal eye diagram near the PHY receiver in both the working and failing conditions. This should tell whether the signal itself is degrading after 4 and 1/2 minutes.

Hi Shane,

This is the high level of the schematic that shows the PHY and the End System connection.

Hi Ed,

Were you able to get an eye diagram from the PHY MDI receivers? 

The block diagram is helpful to see, however it doesn't show details on the MDI connection between the PHY and the fiber module. Can you verify this connection follows the datasheet example?

For my own understanding, how do you split the MII signal from each PHY to two MACs? Is there an MII MUX in this signal path?

Best,

Shane

Hi Shane,

The connection does follow the datasheet example you provided above. 

Yea, I have a MUX stage between the PHY and the MAC.

Best,

ED.

Just FYI: My colleagues said they did the eye diagram on both cases (faulted and working conditions) and they didn't see a difference. 

Receive error and false error counters are based on the MDI side of the PHY. I suspect this is an issue with the MDI Fiber interface or with the power up timings on the DP83822. If the datasheet timings are not met, it can put the PHY into a bad state.

ed meee said:

The process I have during power up is: custom config gets loaded to the config register then I do a soft reset of the PHY and a reset of the clock.

When you do the clock reset, is the clock signal disrupted to the PHY? The clock signal should be stable before the PHY power up sequence and stay stable throughout the PHY operation:

Can you check that your system meets the timing requirements in the DP83822 datasheet for power up?

Best,

Shane