DP83867IS: SyncE Implementation

MUTHUKUMAR PARAMASIVAM

Prodigy 20 points

Part Number: DP83867IS

Tool/software:

Dear TI Team,

Can we do the clock recovery on the MAC side after SGMII on the Slave Ethernet switch? As per the above scheme

Based on assumption that DP83867,

will be transmitting SGMII data towards Eth Switch using MDI recovered clock when resolved as SLAVE during autoneg.

Similarly, when resolved as Master, MDI transmission will be done on the SGMII RX Data recovered clock.

5 months ago

0 Gerome Cacho 5 months ago

TI__Mastermind 39845 points

Hello,

SGMII would primarily be using the local XTAL on the DUT. If you would like to use SyncE, please use Reg 0x170[12:8].

Sincerely,

Gerome

0 MUTHUKUMAR PARAMASIVAM 5 months ago in reply to Gerome Cacho

Prodigy 20 points

Dear TI Team,

To transmit the syncE Timing to the Slave, then the clock, Pin 15, Pin Name: X_I should be connected from System PLL instead of XTAL? on both side

Regards,

Muthukumar

0 Gerome Cacho 5 months ago in reply to MUTHUKUMAR PARAMASIVAM

TI__Mastermind 39845 points

Hello,

This is more application specific. By utilizing Reg 0x170, PHY can recover and present the master clock on the CLKOUT pin which then can be routed to the PLL.

Sincerely,

Gerome

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DP83867IS: SyncE Implementation