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SN65DSI84: problems when use ti-sn65dsi84 to convert raspberry pi cm4 dsi1 to dual-link lvds screen

Part Number: SN65DSI84
Other Parts Discussed in Thread: SN65DSI83

Tool/software:

hello,

we are now develop one product with raspberry pi cm4,

and it has a 1920x1080 dual-link LVDS screen.

we use ti-sn65dsi84 to convert cm4 mipi dsi video output to duall-ink lvds screen

and now meet some problems.

(1) screen flicker after some time

when use dsi 3-lane or 2-lane, even 1-lane, the screen can work correctly. but it's not stable.

after working a long time, sometimes 2-3 days .or sometimes 2-3 weeks, the screen will flicker with multi-color.   just as the video I uploaded.

it's not the screen 's business. we tried to disconnect the screen LVDS interface and replace with another same kind screen, it flicker too.

and if we touch the screen to change the page, it will turn to normal, but can only keep normal for 3-5 seconds, then it flicker again.

why is it happening? and how to solve it?

(2) when use dsi 4-lane, screen shows nothing

we try to use dsi 4-lane, we edit the devicetree data-lanes = <1 2 3 4>; but the screen shows nothing.

I can see the screen correctly with VNC tool, so there must be something wrong in the raspberry dsi signal, or in the sn65dsi84 bridge.

I read the registers value, and seems OK.

and I have read the ti document, use the dsi tunner v2.1 tool to generate CSR value. but still no use.

(3) kernel driver sn65dsi83.c bug?

when compare the dsi tunner CSR value with the ti-sn65dsi84 kernel offical driver value (kernel / driver / gpu / drm / bridge / ti-sn65dsi83.c)

I find that the horizontal porch registers (0x2c 0x34 0x38) are not the same. values in kernel driver are 2-times than the values generated by dsi tunner tool.

REG_VID_CHA_SYNC_DELAY_LOW 0x28

REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34

REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38

and after test, I think the values in dsi tunner tool is correctly, the value generated in ti-sn65dsi83.c is correct for sn65dsi83 single-link lvds , but should be half for sn65dsi84 dual-link lvds.

am I right?

should the kernel driver ti-sn65dsi83.c adjust to be compatible for sn65dsi84?

thanks.

 attachments:

(1) video of screen flicker

(2)screen timing

(3) my linux device tree overlay.dts

/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/bcm2835.h>

/ {
        compatible = "brcm,bcm2835";

        /* PWM0 function */
        fragment@0 {
                target = <&gpio>;
                __overlay__ {
                        pwm_pins: pwm_pins {
                                brcm,pins = <19>;
                                brcm,function = <BCM2835_FSEL_ALT5>; //PWM0_1
                                brcm,pull = <0>;
                        };
                };
        };

        fragment@1 {
                target = <&pwm>;
                frag1: __overlay__ {
                        pinctrl-names = "default";
                        pinctrl-0 = <&pwm_pins>;
                        assigned-clock-rates = <50000000>;
                        status = "okay";
                };
        };

        fragment@2 {
                target-path = "/";
                __overlay__ {
                        //#gpio-cells = <2>;
                        /* Panel backlight through PWM0-1 on GPIO 19 */
                        backlight_lvds: backlight {
                                compatible = "pwm-backlight";
                                pwms = <&pwm 1 1000000 0>; /* Period of 1000000ns means 1KHz */
                                brightness-levels = <0 1000>;
                                num-interpolated-steps = <100>;
                                default-brightness-level = <1>;
                                //enable-gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;     /* Backlight enable */
                        };

                        panel: panel {
                                compatible = "panel-lvds";
                                backlight = <&backlight_lvds>;

                                label = "AUO:G156HAN";

                                /* Physical dimensions of active area */
                                width-mm = <344>;
                                height-mm = <194>;

                                data-mapping = "vesa-24";

                                panel-timing {
                                        /* IF the hactive and porches in the datasheet are used for a single LVDS channel */
                                        /* since we use dual LVDS channel, Horizontal paramter and clock must double*/
                                        //clock-frequency = <141000000>;        //140880000 对应 1920+184
                                        clock-frequency = <125000000>;
                                        hactive = <1920>;
                                        hsync-len = <60>;
                                        hfront-porch = <62>;
                                        hback-porch = <62>;

                                        vactive = <1080>;
                                        vsync-len = <12>;
                                        vfront-porch = <12>;
                                        vback-porch = <12>;
                                };

                                ports {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        port@0 {
                                                reg = <0>;
                                                dual-lvds-odd-pixels;
                                                panel_in_a: endpoint {
                                                        remote-endpoint = <&bridge_out_a>;
                                                };
                                        };
                                        port@1 {
                                                reg = <1>;
                                                dual-lvds-even-pixels;
                                                panel_in_b: endpoint {
                                                        remote-endpoint = <&bridge_out_b>;
                                                };
                                        };
                                };
                        };
                };
        };

        fragment@3 {
                target = <&i2c_csi_dsi>;
                __overlay__ {
                        #gpio-cells = <2>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "okay";

                        bridge@2c {
                                compatible = "ti,sn65dsi84";
                                reg = <0x2c>;
                                enable-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;

                                ports {
                                        #address-cells = <1>;
                                        #size-cells = <0>;

                                        port@0 {
                                                reg = <0>;
                                                bridge_in: endpoint {
                                                        remote-endpoint = <&dsi_out>;
                                                        data-lanes = <1 2 3 4>;
                                                        //data-lanes = <1 2 3>;
                                                };
                                        };

                                        port@2 {
                                                reg = <2>;
                                                bridge_out_a: endpoint {
                                                        remote-endpoint = <&panel_in_a>;
                                                };
                                        };

                                        port@3 {
                                                reg = <3>;
                                                bridge_out_b: endpoint {
                                                        remote-endpoint = <&panel_in_b>;
                                                };
                                        };
                                };
                        };
                };
        };

        fragment@4 {
                target = <&dsi1>;
                __overlay__ {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "okay";
                        port {
                                dsi_out: endpoint {
                                        remote-endpoint = <&bridge_in>;
                                };
                        };
                };
        };

        fragment@5 {
                target = <&i2c0if>;
                __overlay__ {
                        status = "okay";
                };
        };

        fragment@6 {
                target = <&i2c0mux>;
                __overlay__ {
                        status = "okay";
                };
        };
};

(4) my sn65dsi84 regsiters value read from i2c bus, seems OK.

reg \ lane 4 3 2
0xa 85 85 85
0xb 28 38 58
0xd 1 1 1
10 26 2e 36
11 0 0 0
12 4b 64 64
18 c c c
19 5 5 5
1a 3 3 3
1b 0 0 0
20 80 80 80
21 7 7 7
24 38 38 38
25 4 4 4

(5) my dsi tunner v2.1 setting (4-lane)

  • if you can't see the attachment 1 video of screen flicker, the http link is http://jiang.shuang.he.cn/dsi84/video.mp4.

    and attachment 5 the picture is uploaded 4 times repeatly by mistake.

    thank you for your attention and hope your help.

  • Hi Crane,

    1. Is the issue happening on all boards tested? How frequently does it occur?

    And how was the issue captured? Was it continuously recorded? The video did not load here.

    3. When tested with the DSI tuner initialization, was the issue resolved? 

    The initialization for the DSI83 and DSI84 will be different, since they are single-link and dual link LVDS respectively. Where did you receive this kernel driver? The only Linux kernel shared by TI is here: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/546145/question-about-sn65dsi84/

    If you update the driver sequence to be similar to the DSI sequence, is the issue resolved?



    Best regards,
    Ikram


  • hello, thank you for your reply.

    (1). yet we have made over 5 test boards, and almost all boards have this screen flicker issue. (the realVNC desktop is OK)

    we can't reproduce this problem stablely. but we know it will occur at last.

    maybe after 2-3 days, or 1-2 weeks, or even several months.

    it will happen, but we don't know when.

    it will recover to normal if we reboot the system. and after some time, it flicker again.

    the flicker video: flicker_video1.mp4

    -

    (2). why we just edit the devicetree, from 2 or 3 lane to 4 lane, the screen doesn't work again?

    we don't change any other things, only the data-lanes=<1 2 3> or <1 2> to <1 2 3 4> in the devicetree. 

    we think it's better to use all 4 dsi lanes.

    we don't know whether it does matter with the screen flicker issue.

    I notice that the dsi tunner v2.1 tool suggest the input dsi clock < 500M.

    we use 1920x1080 24bpp screen, only 4 lane the dsi clock = 420M < 500M.

    3 lane dsi clock = 560M, 2 lane dsi clock=840M > 500M

    will it be related to the unstable screen flicker? 

    -

    (3) I use the latest linux kernel code cloned from github raspberry, the kernel version is 6.6.x.

    and the driver file kernel/drivers/gpu/drm/bridge/sn65dsi83.c is also the latest.

    the code to set 0x2c 0x34 0x38 is at the function sn65dsi83_atomic_pre_enable(),

    the commented line is  the original code, and the  divide by 2 code lines are mine.

            /* 32 + 1 pixel clock to ensure proper operation */
            le16val = cpu_to_le16(32 + 1);
            regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);
    //      le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start);
            le16val = cpu_to_le16((mode->hsync_end - mode->hsync_start)/2);
            regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
                              &le16val, 2); //0x2c
            le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start);
            regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
                              &le16val, 2);
            regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
    //                   mode->htotal - mode->hsync_end); //0x34
                         (mode->htotal - mode->hsync_end)/2); //0x34
            regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
                         mode->vtotal - mode->vsync_end);
            regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
    //                   mode->hsync_start - mode->hdisplay); //0x38
                         (mode->hsync_start - mode->hdisplay)/2); //0x38
            regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
                         mode->vsync_start - mode->vdisplay);
            regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);

    will the 2-times sync, porch value have relationship with the (1) screen flicker issue?

    we haven't tested enough time yet after I modify the kernel driver.

    -

    thank you.

  • Hi Crane,

    1. When the issue is reproduced, could you please read the 0xE5 for errors

    2. Since you are using 1920x1080p, what is the pixel clock rate?

    Please use this resolution guide: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945185/faq-sn65dsi84-sn65dsi83-sn65dsi84-and-sn65dsi85-resolution-guide


    PCLK = Htotal x Vtotal x fps
    Assuming standard timings, PCLK = 2200 * 1125 * 60 = 148.5 MHz

    LVDS CLK = (Htotal x Vtotal x fps) /2 = 74.25 MHz

    DSI CLK = (2 x LVDS_CLK x bpp)/(2 x # DSI lanes) = (148.5 MHz x 24)/(2 x # DSI lanes)

    with 4 lanes, DSI CLK = 445.5 MHz
    with 3 lanes, DSI CLK = 594 MHz,  which is not within the 500 MHz limit

    This could be a cause of flickering. Please use 4 DSI lanes here for this video bandwidth
                   

    3. Could you please share a link to where this kernel is from. We would have to check whether this is shared and supported by TI or if it's from an external source.

    The only DSI driver supported for this device is shared here: 
    https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/video/omap2/dss/dsi.c?id=c16fa4f2ad19908a47c63d8fa436a1178438c7e7

    E2E link: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/546145/question-about-sn65dsi84/

    Best regards,
    Ikram

  • (1)

    I have read other regs before, they don't change, just the same value as normal.

    I missed to read the 0xe5 value. I will read its value next time it occurs.

    (2)

    I had read this guide, and use dsi tunner tool to compare the value between driver and the tool,

    and find the (3) horizontal  blanking regs 2-times issue.

    the screen panel-timing table is as I uploaded in the attachment (2) in this post, the suggested LVDS clock is 70.5M,

    LVDS clk is (1920+184) x (1080+36) x 60hz /2 = 70,441,920

    I want to use 4 lane, but when I change the deviceetree, data-lane settings from <1 2 3> to <1 2 3 4>, the screen shows nothing.

    I can see lanes in driver struct is 4, and the sn65dsi84 regs 0x0b DSI_CLK_DIVIDER is divided by 6, 0x10 CHA_DSI_LANES is 4.

    all regs seems right configured, but the screen shows nothing.

    the devicetree is uploaded as attachment (3).

    any suggestions what may be wrong

    (3)

    the kernel is downloaded from raspberry offical github: the website is https://github.com/raspberrypi/linux,

    and I also check the linux source mainline which is located at http://www.kernel.org,

    the sn65dsi83.c driver is the same. there's no sn65dsi84.c, they use the same driver。

  • Hi Crane,

    Please use the DSI tuner to configure the initialization script for this, since you tested with it and it is working. And please use 4 lane MIPI DSI for this resolution to be within the bandwidth.

    Could you share the link to where you got this driver? If it's not from the TI source we shared earlier, we cannot suggest the changes required.

    The only DSI driver supported for this device is shared here: 
    https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/video/omap2/dss/dsi.c?id=c16fa4f2ad19908a47c63d8fa436a1178438c7e7


    We would recommend to use the driver above (if it's applicable) or to use the DSI tuner settings.

    Best regards,
    Ikram

  • Hi Crane,

    Please use the DSI tuner to configure the initialization script for this, since you tested with it and it is working. And please use 4 lane MIPI DSI for this resolution to be within the bandwidth.

    Could you share the link to where you got this driver? If it's not from the TI source we shared earlier, we cannot suggest the changes required.

    The only DSI driver supported for this device is shared here: 
    https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/video/omap2/dss/dsi.c?id=c16fa4f2ad19908a47c63d8fa436a1178438c7e7


    We would recommend to use the driver above (if it's applicable) or to use the DSI tuner settings.

    Best regards,
    Ikram