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SN65DSI86-Q1: Can't Get DP Signal Output

Part Number: SN65DSI86-Q1
Other Parts Discussed in Thread: SN65DSI86, TEST2,

Tool/software:

Hi Team,

Customer try to use the SN65DSI86 EVM and connect it to their MB.

Sometimes they can't get display output.

Configure 0x96 to 0x0A but link training is still off.

Below is their SW setup.

======ASSR RW control ======
<i2c_write addr="0x2D" count="1" radix="16"> FF 7 </i2c_write>/>
<i2c_write addr="0x2D" count="1" radix="16"> 16 1 </i2c_write>/>
<i2c_write addr="0x2D" count="1" radix="16"> FF 0 </i2c_write>/>
======REFCLK Frequency ======
<i2c_write addr="0x2D" count="1" radix="16"> 0A 6 </i2c_write>/>
=====DSI Mode ======
<i2c_write addr="0x2D" count="1" radix="16"> 10 26 </i2c_write>/>
======DSIA Clock ======
<i2c_write addr="0x2D" count="1" radix="16"> 12 59 </i2c_write>/>
======Enable enhanced frame in DSI86 ======
<i2c_write addr="0x2D" count="1" radix="16"> 5A 4 </i2c_write>/>
======Number of DP lanes ======
<i2c_write addr="0x2D" count="1" radix="16"> 93 30 </i2c_write>/>
======DP Datarate ======
<i2c_write addr="0x2D" count="1" radix="16"> 94 E0 </i2c_write>/>
======Enable PLL ======
<i2c_write addr="0x2D" count="1" radix="16"> 0D 1 </i2c_write> <sleep ms="10"/>
======Start Semi-Auto Link Training ======
<i2c_write addr="0x2D" count="1" radix="16"> 96 0A </i2c_write> <sleep ms="20"/>
======CHA Active Line Length 1920======
<i2c_write addr="0x2D" count="2" radix="16"> 20 80 07 </i2c_write>/>
======Vertical Active Size 1080======
<i2c_write addr="0x2D" count="2" radix="16"> 24 38 04 </i2c_write>/>
======Horizontal Pulse Width ======
<i2c_write addr="0x2D" count="2" radix="16"> 2C 2C 00 </i2c_write>/>
======Vertical Pulse Width ======
<i2c_write addr="0x2D" count="2" radix="16"> 30 05 80 </i2c_write>/>
======HBP ======
<i2c_write addr="0x2D" count="1" radix="16"> 34 94 </i2c_write>/>
======VBP ======
<i2c_write addr="0x2D" count="1" radix="16"> 36 24 </i2c_write>/>
===== HFP ======
<i2c_write addr="0x2D" count="1" radix="16"> 38 58 </i2c_write>/>
===== VFP ======
<i2c_write addr="0x2D" count="1" radix="16"> 3A 04 </i2c_write>/>
===== DP-18BPP Disable ======
<i2c_write addr="0x2D" count="1" radix="16"> 5B 0 </i2c_write>/>
===== Enhanced Frame, and Vstream Enable ======
<i2c_write addr="0x2D" count="1" radix="16"> 5A 0C </i2c_write>/>

They also have the SN65DSI86-Q1 on the board, in previous case study, we need to pull TEST2 pin HIGH then we can configure the 0x5A to 0xC.

But we found some board still failed to output DP even we already Pull TEST2 pin high.

And turns out the 0x5A is still read only, and we get 0xD value.

Wondering what could cause this phenomenon.

-> Pull TEST2 pin HIGH -> Set 0x16[0] -> Pull EN HIGH

Here's the F0~F8 Error register we got:

Could you help to check and share your comment with us?

Thank you.

  • Hi Evan,

    Does writing to the 0x5A register work when the system is working? Is it only in the not working cases that it does not write?

    Could you verify the TEST2 and EN pin power-up sequence? Is it possible that it's not pulled high during the EN rising edge?

    When the system is working, do the 0xF0 - 0xF8 registers show the same values? Are there other errors showing on these registers in the not working cases? It would help to know if the issue is always the same.


    Best regards,
    Ikram

  • Hi Ikram,

    Thank you for the sharing.

    We already clarify that it's sequence problem among TEST2 & EN pin.

    Close this case now.