TL16C752D: Some questions

Ryu Yamashita said:

Differences between TL16C752D and TL16C752C

D version is a fix to the short stop bit errata and also an update to the newer process technology.

Ryu Yamashita said:

Should the trigger level for the transmit FIFO be specified by the number of empty buffer sizes?
Or should it be specified by the number of data to be sent?

The trigger should be based on the number of available spots in the FIFO, so setting it to 8 spaces means when 8 or more bytes are open the trigger will set. 64 - 8 = 56 so 57 bytes or more bytes deasserts TXRDY. If Bytes in TX FIFO reaches 56 bytes or less then TXRDY will assert (user can add 8 more bytes). So set it to the number of empty spaces you want for the TXRDY interrupt.

Ryu Yamashita said:

Does an interrupt occur when the number of data to be sent or the number of empty buffer sizes reaches (equals) the number of trigger levels?
Does an interrupt occur when the trigger level is exceeded?

Yes, if you have the interrupt enabled then the interrupt should occur at or above the trigger level. (The INT should occur around the same time as the TXRDY flag.

Ryu Yamashita said:

If a transmission is performed with only the number of transmit data in the transmit FIFO that does not exceed the trigger level, interrupts that exceed the transmit trigger level will not be generated.
Is it correct to assume that a transmit empty interrupt is generated for a transmission that does not exceed the trigger level?

It's based on spaces available so an interrupt should trigger if you are below the available space left. 

Ryu Yamashita said:

After an interrupt that crosses the transmit FIFO trigger level is received and the interrupt is released by reading the ISR register, will the transmit empty interrupt be received?

Yes, it should clear the IIR and INT should de-assert if other interrupt sources are not flagged. (So you could potentially get an INT, then go to read the register and no interrupt source is identified then INT de-asserts, in this case you would need to assume the INT source flag was taken care of before the processor could address the INT)

Ryu Yamashita said:

Is it correct to assume that when Auto RS485 mode is enabled and 485LG is OFF, the interrupt by the FIFO trigger level will not be triggered?

This sounds like the case, based on your follow up question. I think in this mode, you're expected to load the TX FIFO up to 64 bytes and let it go without refilling. 

Ryu Yamashita said:

When Auto RS485 mode is enabled, if 485LG is ON, interrupts are triggered by the FIFO trigger level, but not the transmit complete (TSR empty) interrupt, but the empty (THR empty) interrupt, is this correct?

This one I'm not entirely sure about. Datasheet seems to indicate that it's an or condition where below below the threshold triggers an INT (which should already occur) but also crossing the threshold cases an INT. My interpretation of this is being at or below the threshold causes the INT. So the device operates like when it wasn't in the RS485 mode (points back to your previous question).

Ryu Yamashita said:

Although not made by TI, the following Errata was found in a serial controller from another company.
(Errata contents) When a transmit interrupt is received at the timing when the ISR register is read by the receive interrupt, the transmit interrupt is canceled by reading the ISR register and the transmit interrupt is missed.
Is it safe to assume that there is no such Errata?

I'm not aware of this errata. You should still be able to verify the TX FIFO status by reading LSR5 or checking the TXRDY pin status.

-Bobby

The 754C should use the same IP as the 752C which has a short stop bit errata. It is also in an older process technology. I think there is one other differences but I can't remember what it was. I think in the 752C version the software was not compatible with 752D which would likely carry over to the 754C since the IP is shared. 

-Bobby