Tool/software:
Dear Team,
In order to meet the rise time requirement of t3 for the external circuit of PDB pin，according to datasheet pull up resister 10K，pull down capacitance 1uF.
Now we changed pull down capacitance to 0.1uF, pull up resister 10K no changed.，faster power on time.
Advance the completion time of power on to before reading EEPROM.
Could you please help confirm if the change plan (10K and 0.1uF) is OK?
Hi Zoe,
Thanks.
After modifying the PDB peripheral RC circuit (10K and 0.1uF). During testing and verification, it was found that the VPDB within the red box of the "Specification" in the attachment does not meet the requirement of less than 10% of VDDIO (0.18V).
After testing the modified circuit, when t2 reaches 90%, the voltage of V-PDB is 0.4V, which does not meet the requirement of V-PDB<10% of VDDIO (0.18V), but does not exceed the V-IL set by V-PDB (0.35 * 1.8V=0.63V), and is still in a low level state.
Could you please help confirm if the current peripheral circuit status (10K and 0.1uF) of the PDB point will affect its functionality? Do you need to make any changes? If changes are needed, please provide suggestions.
