I am using the DP83816 Ethernet controller in an embedded application. When looking through the errata for the processor chip-set there is a problem documented for "non-linear" PCI addressing by a PCI bus master. The DP83816 acts as a bus master, performing DMA transfers.
The state of address bits AD1 and AD0 during the address phase of a PCI transfer determine the addressing mode.
AD1 AD0 Addressing Mode
=== === ===============
0 0 Linear incrementing
0 1 Cacheline toggle
1 0 Cacheline wrap
1 1 Reserved
I am trying to find out what addressing mode is used by the DP83816 so that I can determine if the chip-set errata applies. Does the DP83816 use one of the modes other than "Linear incrementing"? Does the DP83816 retry the operation using "Linear incrementing" mode when one of the other modes fails because of being unsupported. The DP83816 has no way to program the cache line size but I'm not sure that implies it is always using "Linear incrementing mode".
Thanks to anyone willing to help me answer this question.
