TIC12400-Q1: Registers refresh time

Hi Daniel,

Daniel Wang (auto) said:

Customer configured the POLL_TIME as 32ms, detection filter configured as least consecutive polling cycles, here are two questions to confirm with you:

1. Will the register SSC be refreshed every 96ms (32ms *3)?

The SSC Interrupt bit will be updated when it is determined an Input pin has changes states and meets the interrupt generation configuration in the registers for that pin.  If a detection filter has been enabled that requires 3 consecutive polling cycles of the new pin state to be detected before generating an interrupt, then yes, it will take 96ms for the SSC bit to be set and an interrupt to be generated.

Daniel Wang (auto) said:

2. How about the DI and ADC registers including IN_STAT_COMP，IN_STAT_ADC0 to IN_STAT_ADC1，ANA_STAT0 to ANA_STAT11, will them be refreshed every 32ms or 96ms?

The IN_STAT_xxxx register will be updated to reflect the most recent polling cycle.  Therefore they will be updated every 32ms based on the POLL_TIME configuration of 32ms.  These registers are independent of the digital filter and interrupt register that contains the SSC bit.

Regards,

Jonathan