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SN75LVDS84A: How to check LVDS output is normal?

Yuxi Liu(Tony)
Expert 3220 points
Part Number: SN75LVDS84A
Other Parts Discussed in Thread: SN75LVDS82, FLINK3V8BT-85

Tool/software:

Hi TIer

My customer use SN75LVDS84A and THC63LVDF84C as RGB to LVDS and LVDS to RGB bridge to screen.

We meet a issue which is DE signal jitter , some time DE signal include more one clk. some time not.

They probe the THC63LVDF84C DE output. But they do the ABA test, we found the issue is follow the SN75LVDS84A.

So do you have some method to check if the LVDS output is correct?

We also probe the DE signal input in SN75LVDS84A, which is good no jitter.

DE at SN75LVDS84A input.

 

DE at THC63LVDF84C output:

  • 0
    TI__Mastermind 23260 points

    Hi Yuxi, 

    If these waveforms are from the boards that show this issue, could you also share the waveforms from the working boards?

    If the LVDS connector (output) of the SN75LVDS84A has cable, then it would be possible to connect it to a Flatlink receiver such as SN75LVDS82 to get the output in parallel data and check DE. This means for testing, the output would be connected to the LVDS82A instead of the "THC63LVDF84C". Does this board have that type of cable connection available? 

    What is the pixel clock frequency used here? Is it within the range for this device?

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    TI__Expert 3220 points

    Hi Ikram Haque

    The waveform is from THC63LVDF84C. So you can see the first is good board. second is bad board. Which have random lower edge, jitter about 1 clock width. 

    Customer don't have SN75LVDS82 , I also see no EVM of SN75LVDS82 on ti. com . Do you have more suggestion?

    They have cable , so I need find a verified TI receiver EVM board, Is there a recommendation for this EVM? Cheers 

    But the customer said they confirmed that the problem was from the transmitter by exchanging different THC63LVDF84C. 

  • 0 in reply to Yuxi Liu(Tony)
    TI__Mastermind 23260 points

    Hi Yuxi,

    1. How is the waveform being captured? Is this edge-triggered and with persistence on? Could you tell us how they are trying to measure jitter here?

     2. The first is the SN75LVDS84A input, which should be good in both working and not-working boards. Could you share the "DE at THC63LVDF84C" for good and NG boards?

    3. What is the frequency of the issue? How many boards tested and how many show this issue? And do the NG boards always show this?

    If this is occurring on many boards tested, then this could be a system design issue rather than issue with the part itself. Also, what is the PCLK rate?

    4. They could use one of these https://www.ti.com/tool/FLINK3V8BT-85 FLINK3V8BT-85 EVMs. There is a converter for LVDS to RGB/LVCMOS to check the DE output separately.

    Since DE is serialized on the LVDS lines it is difficult to check the DE bit there directly. The best way would be to use one of these FLINK boards to get parallel output data.


    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    TI__Expert 3220 points

    The complete video signal link is the CPU output RGB signal converted to LVDS signal via the SN75LVDS84ADGGR. Connected to the screen end via a screen cable; the screen end has a bridge chip THC63LVDF84C, which then converts the LVDS signal into an RGB signal output to the driver IC of the screen. 

    1. How is the waveform being captured? Is this edge-triggered and with persistence on? Could you tell us how they are trying to measure jitter here?

    Condition triggered, DE rising edge start is event A, CLK falling edge is event B, screen resolution is 800*480, The anomaly is that the bottom line of pixels on the screen displays erratically and flickens. So the trigger time is set to 800, and this is persistence mode open. The normal display should be only one  DE down edge, and an anomaly display will more one clock for before DE signal.

    Bad DE at THC63LVDF84C output:



     2. The first is the SN75LVDS84A input, which should be good in both working and not-working boards. Could you share the "DE at THC63LVDF84C" for good and NG boards?

    Yes , SN75LVDS84A input looks good.

    The board of the NG will contain an additional clock sometime because persistence mode we can see two down edge , like the white box in the figure.

    good board not.



    3. What is the frequency of the issue? How many boards tested and how many show this issue? And do the NG boards always show this?

    10% NG not only one.



    If this is occurring on many boards tested, then this could be a system design issue rather than issue with the part itself. Also, what is the PCLK rate?

    PCLK = 44.44Mhz in both normal and anomaly case. same waveform we see.

    bad :

    good:


    4. They could use one of these https://www.ti.com/tool/FLINK3V8BT-85 FLINK3V8BT-85 EVMs. There is a converter for LVDS to RGB/LVCMOS to check the DE output separately.

    Already ship.

  • 0 in reply to Yuxi Liu(Tony)
    TI__Mastermind 23260 points

    Thank you Yuxi,

    Yuxi Liu(Tony) said:
    DE at SN75LVDS84A input.

    Are the "DE at SN75LVDS84A input" measurements also with persistence on and it always aligns this way with the input clock? It would help to check whether there is any misalignment from the SoC/ source side.

    If possible, can they also try with a different timing/ resolution and check if this issue still occurs? They could try with a slower PCLK rate, or a different display timing is there another display available.


    It will help to test with the FLINK board to verify whether the same issue occurs with a different receiver device. 

    Thank you,
    Ikram