Part Number: DS90UB940-Q1
Tool/software:
Hello Team,
My customer questioned how they can calculate MIPI CSI output speed.
As I understand, PCLK*24bit(RGB888)/lane counts would be CSI speed. So I think it may be PCLK*6(=24bit/4). but datasheet doesn't say so. it says x7 of PCLK in case 4lane counts.
Can you explain why CSI output speed is x7 of PCLK in condition of 4lanes??
Thank you.
Hi Harry,
Thanks for your patience.
Based on the CSI-2 specification, CSI-2 has a clock frequency of 3.5x PCLK frequency for 4-lane MIPI and 7x PCLK frequency for 2-lane MIPI.
Since the CSI datarate = 2 x CSI_CLK, in the case of 4-lane MIPI, we get the following equation CSI datarate = 2 x PCLK x 3.5 = 7 * PCLK
See section 7.4.3 of DS90UH940 datasheet below:
Thanks,
Ragav Subramanian
Hello Ragav,
I don't think it is correct.
CSI uses DDR clock. So it would consider total data throughput. Here are MIPI CSI/DPHY spec.
Total data throughput=PCLK*bits per pixel
And clock rate is also dependent on lane count. so clock rate=throughput/lane count. so 24bit case, CSI clock speed= PCLK*24/4(lane counts)/2(DDR clock rate)=PCLK*3
Would you pls check with team internally?
Thank you.
