Other Parts Discussed in Thread: SN65DP159,
Tool/software:
Hi
We are planning to use TMDS1204RNQR with Versal FPGA for HDMI TX and RX. We have only 3 channels each of GTY transceivers for TX and RX.
Regarding TX: Data pairs we can map to 3 GTY TX channels, however for clock we need to see how to source this. Please let us know the IN_CLKN clock frequency.
Regarding RX: we want to know if retimer is required for RX. If used for RX is RCLKOUTN is mandatory to be used or OUT_CLK can be used as input to GTY Ref clock? Can RCLKOUTN/P be left NC when the retimer is used as sink? please let us know.