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TUSB8041EVM: Crystal Load Capacitance Mismatch on TUSB8041RGC EVM

Part Number: TUSB8041EVM

Tool/software:

Dear TI Support,

I’m currently designing with the TUSB8041RGC and while analyzing the schematic of the TUSB8041RGC EVM (REV D), I noticed a mismatch regarding the crystal load capacitors.

In the EVM design, C1 and C2 are each 18 pF.

However, the crystal used in the design has a load capacitance (CL) of 20 pF according to its datasheet.

When I apply the standard formula:

C1=C2=2×(CL−Cparasitic)C1 = C2 = 2 \times (CL - C_{parasitic})C1=C2=2×(CLCparasitic)

The result I get is 32 pF, assuming 4 pF of typical parasitic capacitance. That’s quite different from the 18 pF used in the EVM.

Can you help clarify:

  • Was a much higher parasitic capacitance assumed in this layout?

  • Is the 18 pF a mistake or intentional?

  • Should I really be using something like 32 pF in my design?

Thanks in advance for your clarification.

  • HI  Adam:

        Cparasitic include device  parasitic capacitance and board  parasitic capacitance, it's about 8-10 pF. so C1/C2 is between 20-24pF.

       So 18pF is not mistake, 32pF is too higher  for the design.

    Best

    Brian

  • Hi Brian,

    Thank you again for your earlier clarification.

    While reviewing TI’s recommendation of 8–10 pF parasitic capacitance for the TUSB8041RGC EVM, I noticed that ECS — one of the major crystal manufacturers — states in their official load capacitance calculator (https://ecsxtal.com/crystal-load-capacitance-calculator/) that the typical parasitic capacitance is assumed to be around 2–5 pF, including PCB and device parasitics.

    Compared to that, 8–10 pF seems quite a bit higher.
    Could you please clarify:

    • Was there something specific in the TUSB8041RGC EVM layout or input structure that required assuming a higher parasitic value?

    • Or is this just a conservative value used for general robustness?

    Thanks for your insights,

  • Was there something specific in the TUSB8041RGC EVM layout or input structure that required assuming a higher parasitic value?

    nothing specific for our EVM board, it's just conservative value.

    Best

    Brian

  • Hi Brian,

    Thanks again for your reply regarding the parasitic capacitance.

    As a follow-up, I’d like to confirm whether the crystal we are planning to use — TSX-3225_24.0000MF18X-C0 — is fully suitable for the TUSB8041RGC.

    Also, considering that our layout is quite compact and we estimate the parasitic capacitance to be around 5 pF, we are thinking of using C1 = C2 = 26 pF to match the 18 pF load capacitance of the crystal.

    Would you consider this a reasonable approach?

    Thanks for your insights as always.

    Best regards,

  • Since three is no recommendation in datasheet, I prefer to use 22pF or 24 pF.

    Best

    Brian

  • Hi Brian,

    I’m trying to finalize my design using the TUSB8041RGC and I really need a clear answer regarding the crystal selection.

    The part I’m using is: TSX-3225 24.0000MF18X-C0
    Its load capacitance (CL) is 18 pF.

    Can you please confirm:

    1. Is this crystal fully compatible with the TUSB8041RGC?

    2. If yes, what exact values should I use for C1 and C2?

    To be honest, I’m quite confused with the previous answers — there’s no clear recommendation in the datasheet and your replies so far feel more like personal preference than technical confirmation.

    I’d really appreciate a precise and direct answer so I can move forward confidently.

    Thanks for your support.

  • We build our EVM based on TI crystal user guide, which estimate Cboard and Cdevice separately,

    Cboard  is 3-6pf and Cdevcie is 2-5pf, typical  Cboard  + Cdevcie  = 8pf.

    If Cl is 20pf, then C1/C2 =( Cl-8pf) x2=24pf

    Best

    Brian