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TRSF3232E: The receiver is experiencing abnormal operation.

Part Number: TRSF3232E

Tool/software:

During the application process of TRSF3232EIPWR, it was discovered that when PIN 13 and PIN 8 do not receive a signal from the host (with the external wiring harness of the board connector left floating, maintaining a low level), PIN 12 and PIN 9 produce abnormal waveforms as shown in the attachment.

                 

  • What do you mean with "low level"? When the bus is not driven, it should not be negative but at 0 V.

    Please show both the RIN and ROUT voltages at the same time.

  • JY,

    Do you have a schematic we can review?

    The RIN pins are inputs so it is more likely that the signals being probed are generated by the RS232 output. 

    As Clemens commented, if this is the RIN pins with no output connected to it, then we should expect this signal to be GND because of the 5k pull down internal to it. 

    -Bobby

  • Sorry for the misunderstanding. When I say low level, I mean logical low, which is 0V.The RS232 side was always 0V when it was tested, and now the motherboard has been replaced with a new TRSF3232EIPWR, and it can't be re-measured, sorry

  • Sure,this is my schematic about RS232.

  • On the RS-232 bus, "mark" = −15 V…−3 V corresponds to logic high (ROUT = 3.3 V); "space" = +15 V…+3 V corresponds to logic low (ROUT = 0 V).
    0 V would be invalid on the bus, but is used to detect an unplugged driver, and also results in ROUT high.

    Your schematic looks OK.

    If changing the chip solved it, then it is likely that the old chip got damaged (likely by overvoltage/ESD), or that there was a solder error.

  • After replacing the chip, the function has returned to normal. And among the sixteen motherboards, only this one had a faulty TRSF3232EIPWR, so we would like to conduct a failure analysis on this chip. Could you provide information on TI's fees and turnaround time for failure analysis? By the way, we purchased this chip from Mouser.

  • JY,

    Are the ESDs populated on your PCB? I think the unidirectional ESD can forward bias since the RS232 side swings to a negative voltage. So if you have those populated, your positive signal load will clip (when the TTL side is a logic high making the RS232 negative). I'm not sure if this would cause damage to the chip (I don't think it would but it may make the V- charge pump rail sag while it tries to charge it back up).

    Could you provide information on TI's fees and turnaround time for failure analysis? By the way, we purchased this chip from Mouser.

    We don't offer this service for a fee but at the same time TI does not accept all requests for failure analysis. Failure analysis is typically done when devices are suspected of having quality related issues. Based on the current information, I'm not sure it would get accepted for a quality return/check.

    -Bobby

  • I think you are correct. My schematic mistakenly used a unidirectional ESD device for protection, which could indeed lead to operational anomalies with a certain probability. Thank you for pointing out the error.