• State TI Thinks Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 5 answers
  • Subscribers 35 subscribers
  • Views 307 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TCA9554: Power down behaviour

Urban Mueller
Prodigy 70 points
Part Number: TCA9554


Tool/software:

Hi

What happens if the TCA9554's power is removed but there are active signals (3.3V CMOS) driving the I/O pins?
Are the I/O pins high impedance then or do they draw current through the I/O pins?

Thanks for your help!

  • 0
    Guru 318050 points

    The IIOK specification implies that the I/O pins have clamping diodes to VCC. In any case, current can leak through the internal pull-up resistors.

  • 0
    TI__Guru 50898 points

    Hi Urban,

    Please see CLemens response. 

    Regards,

    Tyler

  • 0 in reply to Clemens Ladisch
    Prodigy 70 points

    Yes, but is the clamping to Vcc active in powerdown? If powered and configured as input, the clamping is not active (5V-tolerant with Vcc=3.3V).

  • 0 in reply to Urban Mueller
    TI__Guru 50898 points

    Hi Urban,

    On a second note, this device does not seem to have a positive clamping diode on the I/O when referencing section 6.3 recommended operating conditions. 

    The Voltage at P7-P0 can be up to 5.5V when VCC = 3V (min). 

    Current will still leak through 100k PU, but the current will be small. 

    Whether power up or power down, this shouldn't affect the pin to VCC diode if there was one. In this device, it doesn't seem like there is a positive facing ESD diode from Pxx pin to VCC. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 70 points

    Hi Tyler
    I think the upper FET makes the clamping to Vcc if the port is configured as output. So it depends how this FET behaves in powerdown.
    From datasheet:
    "8.3.1 I/O Port
    When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak
    pull-up (100 kΩ typical) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V, however it
    must be noted that because of the integrated 100 kΩ pull-up resistor it may result in current flow from I/O to VCC
    pin (Figure 15).
    If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In
    this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage
    applied to this I/O pin must not exceed the recommended levels for proper operation."

    Regards,
    Urban

  • 0 in reply to Urban Mueller
    TI__Guru 50898 points

    Hi Urban,

    Your explanation makes sense and is in-line with the datasheet. 

    In power-off the I/O's should not be configured to output. Therefore, the i/o will only have a diode from GND to pin and a 100kohm PU resistor from pin to VCC. No positive clamping diode unless the device is powered up and I/O is configured to output HIGH. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Prodigy 70 points

    Ok, thank you Clemens and Tyler!

  • 0 in reply to Urban Mueller
    TI__Guru 50898 points

    Hi Urban,

    You're welcome. Please let me know if you have any more questions. 

    Regards,

    Tyler