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TMDS1204: TMDS1204 and Spread Spectrum Clocking

Young Hui
Prodigy 70 points
Part Number: TMDS1204
Other Parts Discussed in Thread: TMDS181

Tool/software:

Hi:

When using the TMDS1204, we encountered issues with FPGA reception while receiving HDMI 2.0 signals, which may be caused by input clock random jitter. This could potentially be due to spread spectrum modulation on the driver side.

Does the TMDS1204 support clock recovery functionality to correct both deterministic jitter and random jitter, thereby providing a clean clock output for FPGA use?

Is the TMDS181 capable of performing the same jitter correction as described above?

Thanks!

  • 0
    TI__Guru**** 178606 points

    Hi,

    The TMDS1204 is a re-driver and it will only clean up ISI-related jitter, but it will not clean up the random jitter or SSC. TMDS1204 will pass the random jitter and SSC from its input to its output.

    The TMDS181 is a re-timer. Its clock and data recovery circuits (CDR) are used to track, sample, and retime the equalized data bit streams. The CDRs are designed with a loop bandwidth to minimize the amount of jitter transfer from the video source to the TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1 MHz will be transferred to the TMDS outputs. Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce the amount of high frequency jitter from the video source.

    Thanks
    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 70 points

    Hi,

    Can I add a repeater (TMDS181) to the current design? If the FPGA receives stable signals, then verify if clock jitter is the cause.

    The final solution is to replace TMDS1204 with TMDS181 to solve the clock jitter issue, but does this mean we can only support HDMI 2.0 now?

    And If we still need to support HDMI 2.1. Are there any retimers IC with CDR circuitry?

    Thanks

  • 0 in reply to Young Hui
    TI__Guru**** 178606 points

    Hi,

    You can place TMDS181 in front of TMDS1204, but this will limit the HDMI operation to HDMI2.0. Unfortunately we do not have a HDMI2.1 re-timer in our product portfolio. 

    Have you tried to disable the SSC and see if the FPGA RX issue can be resolved?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 70 points

    Hi David

    Thanks for your response. The HDMI signal source is a special device, we only captured the clock from the FPGA to random jitter, suspecting the presence of SSC. Therefore, it is necessary to verify the TMDS181's clock signal recovery performance.

    Thanks

  • 0 in reply to Young Hui
    TI__Guru**** 178606 points

    Hi,

    HDMI does not support SSC. Even with TMDS181, the SSC may pass through the TMDS181 and be present at the FPGA input. The SSC may also cause TMDS181 PLL to lose its lock, but this has not been tested before.

    My recommendation if possible is to disable the SSC at the source.

    Thanks

    David