SN65DSI86: SN65DSI86EVM

Hi Thomas,

Could you please check that the DSI settings of DSI source and see if it matches the settings of the DSI86 device? Including settings such as DSI data and clock rates, burst mode, sync mode, etc. This issue could be due to DSI settings not matching and input video not synchronizing to the DSI96.

Could you check that you are following the DSI86 initialization and powerup sequence requirements? Are you also clearing the error registers at the start? Is the LOSS_OF_DP_SYNC_LOCK_ERR the only error occurring? Could you read the 0xF0 - 0xF8 and check if there are other errors?


Another check that you can try is by outputting HSYNC and VSYNC pulses to the DSI86 GPIO pins using register 0x5F and measuring HSYNC and VSYNC frequency from the GPIO pin. 

Are you currently testing on a custom board or a TI EVM?

Best regards,
Ikram

Hello,

we have checked the settings on the dsi source an on the dsi86. We can't find a fault configuration. 

On the GPIOs of the DSI86 we meassured the right frequence of  VSYNC and HSYNC.

We are testing on a own hardware.

Best regards

Hi Thomas,

Ikram Haque said:

Could you read the 0xF0 - 0xF8 and check if there are other errors?

Please share the register dumps and check if there are other errors reported.

And could you share the Hsync Vsync waveforms captures? It would help for us to check the timings.

What DSI settings are set on the source (DSI data and clock rates, burst mode, sync mode, etc)? pLease share the DSI86 device settings and script.

Best regards,
Ikram

Hello Ikram,

after Reset we confirm the Registers 0xF0-0xF8. After this, there is only the error LOSS_OF_DP_SYNC_LOCK_ERR.

The Script of the DSI86:

This is a dump of the Registers of the DSI86, starting with register 0x00 in the upper left corner:

We have put the Hsync and Vsync to the GPIOs. This lokk like this (yellow=VSNC):

I show this in the next answer.

Regards

Thomas

We have put the Hsync and Vsync to the GPIOs. This lokk like this (yellow=VSNC):

Regards

Thomas

Hi Thomas,

Could you share the full display timing values, it would help to check that the timings match with what is programmed.

From your calculations are HSYNC, VSYNC meeting the expected timing requirements? It's difficult to say from the waveforms you shared because it doesn't measure the Htotal timing, or period between Hsync pulses. 

From my understanding, there is no video outputting with the SoC video currently right? Or is the video showing a different error?

Could you also please check the ASSR settings? (E2E reference: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945403/faq-sn65dsi86-sn65dsi86-black-screen-debugging-guide)

Best regards,
Ikram

Hi Ikram,

this are the display timings:

We measured  the timings between HSYNC and VSYNC. We think, the timings are correct.

In the moment the situation lokks like this: On the DSI source is a signal. The Display at the displayport shows no image. It is black. The Diplay says: NO DP Input. When we enable the test-mode on the DSI86, the display shows the test image.

The ASSR settings are correct.

Regards Thomas

Hi Ikram,

now we got a tool to calculate the timings and the configuration of the dsi source. We have chaged this. Now the LOSS_OF_DP_SYNC_LOCK_ERR is gone. 

Now we have Error DPTL_UNEXPECTED_HSYNC_ERR. 

We are going to check the Sync.

Regards Thomas

Hi Thomas,

Yes, please check the DSI configuration as the video might not match the timings. You can use the GPIOs Hsync Vsync outputs and measure the pulse period and total period to check if it matches the expected timings. It might be easier to measure and calculate with a logic analyzer if possible.

Is the Hsync error always occurring? Does the video still show black screen or different observation? Let me know what you find.

Best regards,
Ikram

Hello Ikram,

we have found a error in the grafic controller of the MC. Now all errors on the SN65DSI86 are gone. We meassured the HSYNC and the VSYNC. Both are correct. But on the Display we only see one line vertically. Have yoe a idea whats going wrong?

Regards Thomas

Hi Thomas, 

Could you show us what you are seeing on the display output. You could upload a photo here as well.

And is this occurring consistently every time? It might be related to the DSI or DP timings not matching the source.
On the "SN65DSI86 Register Calculator" file, are you setting all the manual inputs, bits per pixel, DSI settings the same as the SoC configuration?

Could you also share or double check the DSI lane rate, DSI clock frequency.


Are there no errors reported at all? Do the Hsync/Vsync pulse widths and periods match the exact timings of the display?

For example, the period between Hsync pulse should match the period for Htotal. in your case, the Htotal period would be = Htotal pixels * pixel clock period =  1296 pixels * (1 /( 46.5 MHz)) sec = 27.87 micro seconds.

Best regards,
Ikram

Hi Ikram,

after changing the polarity of the DE Signal, we got a flickering picture:

Hi Thomas,

The DE polarity should be set to match the display's settings. 

Could you also please check what we listed in the previous response such as the DSI settings and HS/VS measurement.

Thank you,
Ikram