DS90UH981-Q1: FPD link 4 dual serializer dual de-serializer reducing data rate through link

nathan glatz

Prodigy 70 points

Part Number: DS90UH981-Q1

Tool/software:

Hello,

application: aerospace

Resolution 1280x720 100FPS 24bit color. Low latency required

is it possible to use a dual serilaizer/deserializer approach to reduce the bandwidth of data through the cable?

the cable we trying to run through has has about 1.5G per STP capability. We would like to try running 4x STPs for a display of 1280x720 resolution @100FPS 24bit color. We also have a use case at 1920x1080 100FPS 24bit in the future as well.

4 months ago

0 Nikolas Antonucci 4 months ago

TI__Mastermind 21515 points

Hi Nathan,

Happy to provide support on this matter. Can you please provide me with the full video timings (active and blanking) of the displays you intend to use? The resolutions provided above are only active timings. The exact video timings will allow me to provide the most appropriate solution.

Best,

Nikolas

0 nathan glatz 4 months ago in reply to Nikolas Antonucci

Prodigy 70 points

Hello Nikolas,

we are using 148.5Mhz pixel clock, total pixels, ~1650 x 750

+1 Nikolas Antonucci 4 months ago in reply to nathan glatz

TI__Mastermind 21515 points

Hi Nathan,

Can you clarify where you are getting a 148.5MHz PCLK from? If total pixels is 1650x750, this would correspond with a PCLK of approximately 123.75MHz (1650 * 750 = 123.75MHz).

In any case, this can be accomplished with FPD-Link IV devices. Since this is on the public forum, I'd like to move this discussion internally. Are you able to get in contact with your local TI sales representative or field applications engineer?

Best,

Nikolas

0 nathan glatz 4 months ago in reply to Nikolas Antonucci

Prodigy 70 points

thank you. Ill reach out to field engineer shortly.

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DS90UH981-Q1: FPD link 4 dual serializer dual de-serializer reducing data rate through link