Other Parts Discussed in Thread: ONET8501T, ONET8521T, ONET8531T, ONET8541T, , OPA858, LMH34400, LMH13000, LMH32404, OPA855, LMH32401
Tool/software:
The datasheets for the ONET8501T, ONET8521T, ONET8531T, ONET8541T and ONET8551T indicate "DC Offset Cancellation" in Figure 1 on page 2. The block labeled "AGC and DC Offset Cancellation" controls a current sink on the transimpedance amplifier input. My application involves a larger than normal detector current offset that needs to be compensated for, either within the IC or externally to it.
1. How large a current offset can be compensated for by the ICs internal offset cancellation current sink?
2. Can the transimpedance amplifier's bias configuration accommodate purely AC input into the amp after internal or external offset cancellation?
3. Is the ICs offset cancellation circuitry designed to nominally present zero average current to the transimpedance amplifier circuit input?
4. If the IC offset cancellation functionality is not designed to present zero average current to the transimpedance amplifier input, does it zero the baseline current, i.e. the current corresponding to a zero or space? If not, what does it do?
5. What is the bandwidth of the control loop that cancels offset current?
6 After internal or external offset cancellation, on the negative portion of the AC swing, how much current can be drawn OUT OF the transimpedance amp at the amp's input node without overload or degraded performance from the transimpedance amp itself or from downstream stages?
7. Is the transimpedance amp stage AC coupled to the following voltage gain stage?
8. Is AC coupling employed within the IC at any point between the input and output?
9. Is there any documentation available that describes how the offset cancellation functionality works?
The first question is the most important. Your assistance would be very much appreciated. Hoping to hear from you soon.